ATTINY25-20SUR Atmel, ATTINY25-20SUR Datasheet - Page 44

• Manufacturer Part Number: ATTINY25-20SUR
• Description: MCU AVR 2KB FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3
8.3.1
8.4
44
Internal Voltage Reference
Watchdog Timer
ATtiny25/45/85
Voltage Reference Enable Signals and Start-up Time
Figure 8-6.
ATtiny25/45/85 features an internal bandgap reference. This reference is used for Brown-out
Detection, and it can be used as an input to the Analog Comparator or the ADC.
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in
reference is not always turned on. The reference is on during the following situations:
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling
the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in
8-3 on page
Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different
clock cycle periods can be selected to determine the reset period. If the reset period expires
without another Watchdog Reset, the ATtiny25/45/85 resets and executes from the Reset Vec-
tor. For timing details on the Watchdog Reset, refer to
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can
be very helpful when using the Watchdog to wake-up from Power-down.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in
1. When the BOD is enabled (by programming the BODLEVEL[2:0] Fuse Bits).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
3. When the ADC is enabled.
ACBG bit in ACSR).
CC
49. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The
Watchdog Reset During Operation
“System and Reset Characteristics” on page
CK
Table 8-3 on page
170. To save power, the
49.
Table 8-1
2586M–AVR–07/10
Refer to
Table