ATTINY25-20SUR Atmel, ATTINY25-20SUR Datasheet - Page 16

• Manufacturer Part Number: ATTINY25-20SUR
• Description: MCU AVR 2KB FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.2.1
5.3
16
EEPROM Data Memory
ATtiny25/45/85
Data Memory Access Times
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter-
nal data SRAM in the ATtiny25/45/85 are all accessible through all these addressing modes.
The Register File is described in
Figure 5-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 5-3.
The ATtiny25/45/85 contains 128/256/512 bytes of data EEPROM memory. It is organized as a
separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register. For details see
155.
Data Memory Map
On-chip Data SRAM Access Cycles
Address
clk
Data
Data
WR
CPU
RD
(128/256/512 x 8)
64 I/O Registers
Data Memory
Internal SRAM
Compute Address
32 Registers
“General Purpose Register File” on page
T1
Memory Access Instruction
0x0DF/0x015F/0x025F
0x0000 - 0x001F
0x0020 - 0x005F
0x0060
Address valid
CPU
T2
cycles as described in
Next Instruction
“Serial Downloading” on page
T3
10.
Figure
2586M–AVR–07/10
5-3.