ATTINY25-20SUR Atmel, ATTINY25-20SUR Datasheet - Page 31

• Manufacturer Part Number: ATTINY25-20SUR
• Description: MCU AVR 2KB FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.7
6.3
6.3.1
2586M–AVR–07/10
System Clock Prescaler
Default Clock Source
Switching Time
Table 6-13.
Notes:
The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default
clock source setting is therefore the Internal RC Oscillator running at 8 MHz with longest start-up
time and an initial system clock prescaling of 8, resulting in 1.0 MHz system clock. This default
setting ensures that all users can make their desired clock source setting using an In-System or
High-voltage Programmer.
The ATtiny25/45/85 system clock can be divided by setting the
ter” on page
requirement for processing power is low. This can be used with all clock source options, and it
will affect the clock frequency of the CPU and all synchronous peripherals. clk
and clk
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither the
clock frequency corresponding to the previous setting, nor the clock frequency corresponding to
the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the
new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the
previous clock period, and T2 is the period corresponding to the new prescaler setting.
CKSEL0
0
1
1
1
1
FLASH
1. These options should only be used when not operating close to the maximum frequency of the
2. These options are intended for use with ceramic resonators and will ensure frequency stability
device, and only if frequency stability at start-up is not important for the application. These
options are not suitable for crystals.
at start-up. They can also be used with crystals when not operating close to the maximum fre-
quency of the device, and if frequency stability at start-up is not important for the application.
are divided by a factor as shown in
SUT[1:0]
Start-up Times for the Crystal Oscillator Clock Selection (Continued)
33. This feature can be used to decrease power consumption when the
00
01
10
11
11
Start-up Time from
16K (16384) CK
16K (16384) CK
16K (16384) CK
1K (1024)CK
1K (1024)CK
Power-down
(2)
(2)
Table 6-15 on page
Additional Delay
14CK + 64 ms
14CK + 64 ms
14CK + 4 ms
14CK + 4 ms
from Reset
14CK
“CLKPR – Clock Prescale Regis-
34.
Recommended Usage
Ceramic resonator,
fast rising power
Ceramic resonator,
slowly rising power
Crystal Oscillator,
BOD enabled
Crystal Oscillator,
fast rising power
Crystal Oscillator,
slowly rising power
I/O
, clk
ADC
, clk
CPU
31
,