ATTINY25-20SUR Atmel, ATTINY25-20SUR Datasheet - Page 80

• Manufacturer Part Number: ATTINY25-20SUR
• Description: MCU AVR 2KB FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.9
11.9.1
11.9.2
80
Register Description
ATtiny25/45/85
GTCCR – General Timer/Counter Control Register
TCCR0A – Timer/Counter Control Register A
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization Mode. In this mode, the
value written to PSR0 is kept, hence keeping the Prescaler Reset signal asserted. This ensures
that the timer/counter is halted and can be configured without the risk of advancing during con-
figuration. When the TSM bit is written to zero, the PSR0 bit is cleared by hardware, and the
timer/counter start counting.
• Bit 0 – PSR0: Prescaler Reset Timer/Counter0
When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set.
• Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode
• Bits 5:4 – COM0B[1:0]: Compare Match Output B Mode
The COM0A[1:0] and COM0B[1:0] bits control the behaviour of Output Compare pins OC0A and
OC0B, respectively. If any of the COM0A[1:0] bits are set, the OC0A output overrides the normal
port functionality of the I/O pin it is connected to. Similarly, if any of the COM0B[1:0] bits are set,
the OC0B output overrides the normal port functionality of the I/O pin it is connected to. How-
ever, note that the Data Direction Register (DDR) bit corresponding to the OC0A and OC0B pins
must be set in order to enable the output driver.
When OC0A/OC0B is connected to the I/O pin, the function of the COM0A[1:0]/COM0B[1:0] bits
depend on the WGM0[2:0] bit setting.
the WGM0[2:0] bits are set to a normal or CTC mode (non-PWM).
Table 11-2.
Bit
0x2C
Read/Write
Initial Value
Bit
0x2A
Read/Write
Initial Value
COM0A1
COM0B1
0
0
1
1
COM0A1
Compare Output Mode, non-PWM Mode
TSM
R/W
R/W
7
0
7
0
COM0A0
COM0B0
0
1
0
1
PWM1B
COM0A0
R/W
R
6
0
6
0
Description
Normal port operation, OC0A/OC0B disconnected.
Toggle OC0A/OC0B on Compare Match
Clear OC0A/OC0B on Compare Match
Set OC0A/OC0B on Compare Match
COM1B1
COM0B1
R/W
R
5
0
5
0
Table 11-2
COM0B0
COM1B0
R/W
4
0
R
4
0
shows the COM0x[1:0] bit functionality when
FOC1B
R
3
–
0
R
3
0
FOC1A
R
2
–
0
R
2
0
WGM01
R/W
PSR1
1
0
R
1
0
WGM00
R/W
PSR0
R/W
0
0
0
0
2586M–AVR–07/10
TCCR0A
GTCCR