ATTINY25-20SUR Atmel, ATTINY25-20SUR Datasheet - Page 41

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ATTINY25-20SUR

Manufacturer Part Number
ATTINY25-20SUR
Description
MCU AVR 2KB FLASH 20MHZ 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet

Specifications of ATTINY25-20SUR

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
8. System Control and Reset
8.1
8.2
2586M–AVR–07/10
Resetting the AVR
Reset Sources
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative
Jump – instruction to the reset handling routine. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be placed at these
locations. The circuit diagram in
reset circuitry are given in
Figure 8-1.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-
ferent selections for the delay period are presented in
The ATtiny25/45/85 has four sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the
• Brown-out Reset. The MCU is reset when the supply voltage V
threshold (V
than the minimum pulse length.
Watchdog is enabled.
Reset threshold (V
Reset Logic
BODLEVEL[2:0]
POT
RESET
VCC
).
BOT
Pull-up Resistor
) and the Brown-out Detector is enabled.
“System and Reset Characteristics” on page
FILTER
SPIKE
Figure 8-1
CKSEL[3:0]
Power-on Reset
Reset Circuit
Reset Circuit
SUT[1:0]
Brown-out
Watchdog
Watchdog
Oscillator
Generator
Circuit
Timer
Clock
shows the reset logic. Electrical parameters of the
CK
Register (MCUSR)
MCU Status
DATA BUS
Delay Counters
“Clock Sources” on page
CC
TIMEOUT
is below the Brown-out
170.
R
S
Q
25.
41

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