ATTINY25-20SUR Atmel, ATTINY25-20SUR Datasheet - Page 81

• Manufacturer Part Number: ATTINY25-20SUR
• Description: MCU AVR 2KB FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2586M–AVR–07/10
Table 11-3
mode.
Table 11-3.
Note:
Table 11-4
correct PWM mode.
Table 11-4.
Note:
• Bits 3:2 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bits 1:0 – WGM0[1:0]: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see
COM0A1
COM0B1
COM0A1
COM0B1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR0A or OCR0B equals TOP and COM0A1/COM0B1 is set. In
1. A special case occurs when OCR0A or OCR0B equals TOP and COM0A1/COM0B1 is set. In
shows the COM0x[1:0] bit functionality when the WGM0[2:0] bits are set to fast PWM
this case, the compare match is ignored, but the set or clear is done at BOTTOM. See
PWM Mode” on page 75
this case, the Compare Match is ignored, but the set or clear is done at TOP. See
rect PWM Mode” on page 77
shows the COM0x[1:0] bit functionality when the WGM0[2:0] bits are set to phase
Compare Output Mode, Fast PWM Mode
Compare Output Mode, Phase Correct PWM Mode
COM0A0
COM0B0
COM0A0
COM0B0
0
1
0
1
0
1
0
1
Description
Normal port operation, OC0A/OC0B disconnected.
Reserved
Clear OC0A/OC0B on Compare Match, set OC0A/OC0B at BOTTOM
(non-inverting mode)
Set OC0A/OC0B on Compare Match, clear OC0A/OC0B at BOTTOM
(inverting mode)
Description
Normal port operation, OC0A/OC0B disconnected.
Reserved
Clear OC0A/OC0B on Compare Match when up-counting.
Set OC0A/OC0B on Compare Match when down-counting.
Set OC0A/OC0B on Compare Match when up-counting.
Clear OC0A/OC0B on Compare Match when down-counting.
Table
for more details.
for more details.
11-5. Modes of operation supported by the Timer/Counter
“Modes of Operation” on page
(1)
(1)
74).
“Phase Cor-
“Fast
81