ATTINY25-20SUR Atmel, ATTINY25-20SUR Datasheet - Page 24

• Manufacturer Part Number: ATTINY25-20SUR
• Description: MCU AVR 2KB FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.1.4
6.1.5
6.1.6
24
ATtiny25/45/85
ADC Clock – clk
Internal PLL for Fast Peripheral Clock Generation - clk
Internal PLL in ATtiny15 Compatibility Mode
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
The internal PLL in ATtiny25/45/85 generates a clock frequency that is 8x multiplied from a
source input. By default, the PLL uses the output of the internal, 8.0 MHz RC oscillator as
source. Alternatively, if bit LSM of PLLCSR is set the PLL will use the output of the RC oscillator
divided by two. Thus the output of the PLL, the fast peripheral clock is 64 MHz. The fast periph-
eral clock, or a clock prescaled from that, can be selected as the clock source for
Timer/Counter1 or as a system clock. See
is divided by two when LSM of PLLCSR is set, resulting in a clock frequency of 32 MHz. Note,
that LSM can not be set if PLL
Figure 6-2.
The PLL is locked on the RC oscillator and adjusting the RC oscillator via OSCCAL register will
adjust the fast peripheral clock at the same time. However, even if the RC oscillator is taken to a
higher frequency than 8 MHz, the fast peripheral clock frequency saturates at 85 MHz (worst
case) and remains oscillating at the maximum frequency. It should be noted that the PLL in this
case is not locked any longer with the RC oscillator clock. Therefore, it is recommended not to
take the OSCCAL adjustments to a higher frequency than 8 MHz in order to keep the PLL in the
correct operating range.
The internal PLL is enabled when:
The PLLCSR bit PLOCK is set when PLL is locked.
Both internal RC oscillator and PLL are switched off in power down and stand-by sleep modes.
Since ATtiny25/45/85 is a migration device for ATtiny15 users there is an ATtiny15 compatibility
mode for backward compatibility. The ATtiny15 compatibility mode is selected by programming
the CKSEL fuses to ‘0011’.
ADC
XTAL1
XTAL2
• The PLLE bit in the register PLLCSR is set.
• The CKSEL fuse is programmed to ‘0001’.
• The CKSEL fuse is programmed to ‘0011’.
OSCCAL
OSCILLATORS
OSCILLATOR
8.0 MHz
PCK Clocking System.
LSM
1/2
CLK
4 MHz
8 MHz
is used as system clock.
PCK
Figure
PLLE
PLL
8x
6-2. The frequency of the fast peripheral clock
64 / 32 MHz
DETECTOR
1/4
LOCK
16 MHz
8 MHz
CKSEL[3:0]
PRESCALER
CLKPS[3:0]
2586M–AVR–07/10
SYSTEM
CLOCK
PLOCK
PCK