ATTINY25-20SUR Atmel, ATTINY25-20SUR Datasheet - Page 111

• Manufacturer Part Number: ATTINY25-20SUR
• Description: MCU AVR 2KB FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15. USI – Universal Serial Interface
15.1
15.2
2586M–AVR–07/10
Features
Overview
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The Universal Serial Interface (USI), provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load.
A simplified block diagram of the USI is shown in
refer to
listed in the
Figure 15-1. Universal Serial Interface, Block Diagram
The 8-bit USI Data Register (USIDR) contains the incoming and outgoing data. It is directly
accessible via the data bus but a copy of the contents is also placed in the USI Buffer Register
(USIBR) where it can be retrieved later. If reading the USI Data Register directly, the register
must be read as quickly as possible to ensure that no data is lost.
The most significant bit of the USI Data Register is connected to one of two output pins (depend-
ing on the mode configuration, see
transparent latch between the output of the USI Data Register and the output pin, which delays
Two-wire Synchronous Data Transfer (Master or Slave)
Three-wire Synchronous Data Transfer (Master or Slave)
Data Received Interrupt
Wakeup from Idle Mode
Wake-up from All Sleep Modes In Two-wire Mode
Two-wire Start Condition Detector with Interrupt Capability
“Pinout ATtiny25/45/85” on page
“Register Descriptions” on page
USIDR
USIBR
USISR
USICR
2
4-bit Counter
“USICR – USI Control Register” on page
3
2
1
0
3
2
1
0
D Q
LE
2. Device-specific I/O Register and bit locations are
118.
[1]
TIM0 COMP
Figure 15-1
0
1
Control Unit
Two-wire
For actual placement of I/O pins
Clock
CLOCK
HOLD
DO
DI/SDA
USCK/SCL
120). There is a
(Output only)
(Input/Open Drain)
(Input/Open Drain)
111