ATTINY25-20SUR Atmel, ATTINY25-20SUR Datasheet - Page 155

• Manufacturer Part Number: ATTINY25-20SUR
• Description: MCU AVR 2KB FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.5
2586M–AVR–07/10
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). See below.
Figure 20-1. Serial Programming and Verify
Notes:
After RESET is set low, the Programming Enable instruction needs to be executed first before
program/erase operations can be executed.
Table 20-10. Pin Mapping Serial Programming
Note:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
In
pins dedicated for the internal SPI interface.
Symbol
MOSI
MISO
Table 20-10
SCK
CLKI pin.
above, the pin mapping for SPI programming is listed. Not all parts use the SPI
MOSI
MISO
SCK
Pins
PB0
PB1
PB2
ck
ck
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
RESET
GND
(1)
I/O
O
I
I
VCC
+1.8 - 5.5V
ck
ck
Serial Data out
Serial Data in
Description
Serial Clock
>= 12 MHz
>= 12 MHz
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