ATTINY25-20SUR Atmel, ATTINY25-20SUR Datasheet - Page 68

• Manufacturer Part Number: ATTINY25-20SUR
• Description: MCU AVR 2KB FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.2.1
11.2.2
11.3
11.3.1
11.3.2
68
Timer/Counter0 Prescaler and Clock Sources
ATtiny25/45/85
Registers
Definitions
Internal Clock Source with Prescaler
Prescaler Reset
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit
registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the
Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Inter-
rupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and
OC0B).
set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare
interrupt request.
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing
Timer/Counter0 counter value and so on.
The definitions in
Table 11-1.
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (c) bits located in the
Timer/Counter0 Control Register (TCCR0B).
Timer/Counter0 can be clocked directly by the system clock (by setting the CS0[2:0] = 1). This
provides the fastest operation, with a maximum timer/counter clock frequency equal to system
clock frequency (f
clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e. it operates independently of the Clock Select logic of
Timer/Counter0. Since the prescaler is not affected by the timer/counter’s clock select, the state
CLK_I/O
Constant
BOTTOM
MAX
TOP
/1024.
See “Output Compare Unit” on page 71.
Definitions
Description
The counter reaches BOTTOM when it becomes 0x00
The counter reaches its MAXimum when it becomes 0xFF (decimal 255)
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the
value stored in the OCR0A Register. The assignment depends on the mode of operation
Table 11-1
CLK_I/O
). Alternatively, one of four taps from the prescaler can be used as a
are also used extensively throughout the document.
for details. The Compare Match event will also
CLK_I/O
/8, f
CLK_I/O
/64, f
2586M–AVR–07/10
CLK_I/O
T0
).
/256, or