ATTINY25-20SUR Atmel, ATTINY25-20SUR Datasheet - Page 69

• Manufacturer Part Number: ATTINY25-20SUR
• Description: MCU AVR 2KB FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3.3
2586M–AVR–07/10
External Clock Source
of the prescaler will have implications for situations where a prescaled clock is used. One exam-
ple of a prescaling artifact is when the timer/counter is enabled and clocked by the prescaler (6 >
CS0[2:0] > 1). The number of system clock cycles from when the timer is enabled to the first
count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8,
64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program
execution.
An external clock source applied to the T0 pin can be used as timer/counter clock (clk
pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
equivalent block diagram of the T0 synchronization and edge detector logic. The registers are
clocked at the positive edge of the internal system clock (
high period of the internal system clock.
The edge detector generates one clk
(CS0[2:0] = 6) edge it detects.
Figure 11-2. T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T0 has been stable for at least one
system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (following the Nyquist sampling theorem). However, due to variation of the system clock
frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) toler-
ances, it is recommended that maximum frequency of an external clock source is less than
f
An external clock source can not be prescaled.
clk_I/O
Tn
clk
/2.5.
I/O
D
LE
Q
ExtClk
Synchronization
D
< f
clk_I/O
Q
/2) given a 50/50% duty cycle. Since the edge detector uses
T
0
pulse for each positive (CS0[2:0] = 7) or negative
clk
I/O
D
). The latch is transparent in the
Figure 11-2
Q
Edge Detector
shows a functional
T0
). The T0
Tn_sync
(To Clock
Select Logic)
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