ATMEGA64M1-AU Atmel, ATMEGA64M1-AU Datasheet - Page 168

• Manufacturer Part Number: ATMEGA64M1-AU
• Description: IC MCU AVR 64K FLASH 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

19.3.5
19.3.5.1
19.3.5.2
19.3.5.3
168
ATmega16M1/32M1/64M1
Errors
Error at Message Level
Error at Bit Level
Error Signalling
Figure 19-4. Bus Arbitration
The CAN protocol signals any errors immediately as they occur. Three error detection mecha-
nisms are implemented at the message level and two at the bit level:
If one or more errors are discovered by at least one node using the above mechanisms, the cur-
rent transmission is aborted by sending an "error flag". This prevents other nodes accepting the
message and thus ensures the consistency of data throughout the network. After transmission
of an erroneous message that has been aborted, the sender automatically re-attempts
transmission.
• Cyclic Redundancy Check (CRC)
• Frame Check
• ACK Errors
• Monitoring
• Bit Stuffing
The CRC safeguards the information in the frame by adding redundant check bits at the
transmission end. At the receiver these bits are re-computed and tested against the received
bits. If they do not agree there has been a CRC error.
This mechanism verifies the structure of the transmitted frame by checking the bit fields
against the fixed format and the frame size. Errors detected by frame checks are designated
"format errors".
As already mentioned frames received are acknowledged by all receivers through positive
acknowledgement. If no acknowledgement is received by the transmitter of the message an
ACK error is indicated.
The ability of the transmitter to detect errors is based on the monitoring of bus signals. Each
node which transmits also observes the bus level and thus detects differences between the
bit sent and the bit received. This permits reliable detection of global errors and errors local to
the transmitter.
The coding of the individual bits is tested at bit level. The bit representation used by CAN is
"Non Return to Zero (NRZ)" coding, which guarantees maximum efficiency in bit coding. The
synchronization edges are generated by means of bit stuffing.
CAN bus
node A
TXCAN
node B
TXCAN
SOF
SOF
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Arbitration lost
Node A loses the bus
Node B wins the bus
RTR IDE
- - - - - - - - -
8209D–AVR–11/10