ATMEGA64M1-AU Atmel, ATMEGA64M1-AU Datasheet - Page 208

• Manufacturer Part Number: ATMEGA64M1-AU
• Description: IC MCU AVR 64K FLASH 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

20.5.5.2
20.5.6
20.5.6.1
20.5.6.2
208
ATmega16M1/32M1/64M1
Bit Timing
Busy Signal in UART Mode
Baud rate Generator
Re-synchronization in LIN Mode
When the busy signal is set, some registers are locked, user writing is not allowed:
If the busy signal is set, the only available commands are:
Note that, if another command is entered during busy signal, the new command is not validated
and the LOVRERR bit flag of the LINERR register is set. The on-going transfer is not
interrupted.
During the byte transmission, the busy signal is set. This locks some registers from being
written:
The busy signal is not generated during a byte reception.
The baud rate is defined to be the transfer rate in bits per second (bps):
Equation for calculating baud rate:
Equation for setting LINDIV value:
Note that in reception a majority vote on three samplings is made.
When waiting for Rx Header, LBT[5..0] = 32 in LINBTR register. The re-synchronization begins
when the BREAK is detected. If the BREAK size is not in the range (11 bits min., 28 bits max. —
13 bits nominal), the BREAK is refused. The re-synchronization is done by adjusting LBT[5..0]
value to the SYNCH field of the received header (0x55). Then the PROTECTED IDENTIFIER is
sampled using the new value of LBT[5..0]. The re-synchronization implemented in the controller
tolerates a clock deviation of ±20% and adjusts the baud rate in a ±2% range.
• “LIN Control Register” - LINCR - except LCMD[2..0], LENA & LSWRES
• “LIN Baud Rate Registers” - LINBRRL & LINBRRH
• “LIN Data Length Register” - LINDLR
• “LIN Identifier Register” - LINIDR
• “LIN Data Register” - LINDAT
• LCMD[1..0] = 00
• LENA = 0 and/or LCMD[2] = 0, the kill command is taken into account immediately
• LSWRES = 1, the reset command is taken into account immediately
• “LIN Control Register” - LINCR - except LCMD[2..0], LENA & LSWRES
• “LIN Data Register” - LINDAT
• BAUD: Baud rate (in bps)
• clk
• LDIV[11..0]: Contents of LINBRRH & LINBRRL registers - (0-4095), the pre-scaler receives
• LBT[5..0]: Least significant bits of - LINBTR register- (0-63) is the number of samplings in a
clk
LIN or UART bit (default value 32)
i/o
i/o
: System I/O clock frequency
as input clock
b
, the abort command is taken into account at the end of the byte
BAUD =
LDIV[11..0] = (
f
clk
i/o
/ LBT[5..0] x (LDIV[11..0] + 1)
f
clk
i/o
/ LBT[5..0] x BAUD ) - 1
8209D–AVR–11/10