ATMEGA64M1-AU Atmel, ATMEGA64M1-AU Datasheet - Page 59

• Manufacturer Part Number: ATMEGA64M1-AU
• Description: IC MCU AVR 64K FLASH 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

12. External Interrupts
12.1
8209D–AVR–11/10
Pin Change Interrupt Timing
The External Interrupts are triggered by the INT3:0 pins or any of the PCINT23:0 pins. Observe
that, if enabled, the interrupts will trigger even if the INT3:0 or PCINT23:0 pins are configured as
outputs. This feature provides a way of generating a software interrupt. The pin change interrupt
PCI2 will trigger if any enabled PCINT23:16 pin toggles. The pin change interrupt PCI1 will trig-
ger if any enabled PCINT14:8 pin toggles. The pin change interrupt PCI0 will trigger if any
enabled PCINT7:0 pin toggles. The PCMSK3, PCMSK2, PCMSK1 and PCMSK0 Registers con-
trol which pins contribute to the pin change interrupts. Pin change interrupts on PCINT26:0 are
detected asynchronously. This implies that these interrupts can be used for waking the part also
from sleep modes other than Idle mode.
The INT3:0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as
indicated in the specification for the External Interrupt Control Register A – EICRA. When the
INT3:0 interrupts are enabled and are configured as level triggered, the interrupts will trigger as
long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT3:0
requires the presence of an I/O clock, described in
page
rupt can be used for waking the part also from sleep modes other than Idle mode. The I/O clock
is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in
An example of timing of a pin change interrupt is schown in Figure 12-1.
Figure 12-1. Timing of a pin change interrupts
“Clock Systems and their Distribution” on page
PCINT[i]
27. Low level interrupt on INT3:0 is detected asynchronously. This implies that this inter-
pin
clk
pcint_set/flag
PCINT[i] pin
pcint_in[i]
pcint_syn
pin_sync
pin_lat
D
LE
PCIF
clk
Q
n
pin_lat
D
Q
pin_sync
(of PCMSK
PCINT[i] bit
n
)
pcint_in[i]
ATmega16M1/32M1/64M1
27.
0
7
“Clock Systems and their Distribution” on
clk
D
Q
pcint_sync
D
Q
pcint_set/flag
D
Q
(interrupt
PCIF
flag)
n
59