ATMEGA64M1-AU Atmel, ATMEGA64M1-AU Datasheet - Page 303

• Manufacturer Part Number: ATMEGA64M1-AU
• Description: IC MCU AVR 64K FLASH 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

27.10.1
8209D–AVR–11/10
Serial Programming Algorithm
Figure 27-10. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATmega16M1/32M1/64M1, data is clocked on the rising edge of
SCK.
When reading data from the ATmega16M1/32M1/64M1, data is clocked on the falling edge of
SCK. See
To program and verify the ATmega16M1/32M1/64M1 in the serial programming mode, the fol-
lowing sequence is recommended (See four byte instruction formats in
305):
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”
Enable serial instruction to pin MOSI
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. V
Figure 27-11 on page 305
XTAL1 pin
CC
- 0.3V < AVCC < V
MOSI_A
MISO_A
SCK_A
CC
ck
ck
CC
and GND while RESET and SCK are set to “0”. In some sys-
< 12MHz, 3 CPU clock cycles for f
< 12MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 1.8V - 5.5V
for timing details.
XTAL1
RESET
GND
(1)
ATmega16M1/32M1/64M1
AVCC
VCC
+1.8V - 5.5V
+1.8V - 5.5V
(2)
ck
ck
>= 12MHz
>= 12MHz
Table 27-18 on page
303