AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 1196

• Manufacturer Part Number: AT91SAM9G45-CU-999
• Description: IC MCU ARM9 APMC 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

49.2
49.2.1
49.2.1.1
49.2.2
49.2.2.1
49.2.2.2
49.2.2.3
49.2.2.4
49.2.3
49.2.3.1
1196
Errata
AT91SAM9G45
Boot ROM
Error Corrected Code Controller (ECC)
Pulse Width Modulation Controller (PWM)
Boot ROM: NAND Flash boot does not support ECC Correction
ECC: Computation with a 1 clock cycle long NRD/NWE pulse
Uncomplete parity status when error in ECC parity
Unsupported ECC per 512 words
Unsupported hardware ECC on 16-bit Nand Flash
PWM: Zero Period
The boot ROM allows booting from block 0 of a NAND Flash connected on CS3. However, the
boot ROM does not feature ECC correction on a NAND Flash.
Most of the NAND Flash vendors do not guarantee anymore that block 0 is error free. Therefore
we advise to locate the bootstrap program into another device supported by the boot ROM
(DataFlash, Serial Flash, SDCARD or EEPROM), and to implement a NAND Flash access with
ECC.
None.
If the SMC is programmed with NRD/NWE pulse length equal to 1 clock cycle, HECC can't com-
pute the parity.
It is recommended to program SMC with a value superior to 1.
When a single correctable error is detected in ECC value, the error is located in ECC Parity reg-
ister's field which contains a 1 in the 24 least significant bits except when the error is located in
the 12th or the 24th bit. In this case, these bits are always stuck at 0.
A Single correctable error is detected but it is impossible to correct it.
None.
1 bit ECC per 512 words is not functional.
Perform the ECC computation by software.
Hardware ECC on 16-bit Nand Flash is not supported.
Perform the ECC by software.
It is impossible to update a period equal to 0 by using the PWM_CUPD register.
None
Problem/Fix Workaround
Problem/Fix Workaround
Problem/Fix Workaround
Problem/Fix Workaround
Problem/Fix Workaround
Problem/Fix Workaround
6438F–ATARM–21-Jun-10