AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 267

• Manufacturer Part Number: AT91SAM9G45-CU-999
• Description: IC MCU ARM9 APMC 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

22.7.5
Name:
Access:
Reset:
This register can only be written if the bit WPEN is cleared in
• TRFC: Row Cycle Delay
Reset Value is 8 cycles.
This field defines the delay between a Refresh and an Activate command or Refresh command in number of cycles. Num-
ber of cycles is between 0 and 31
• TXSNR: Exit Self Refresh Delay to Non-read Command
Reset Value is 8 cycles.
This field defines the delay between cke set high and a non Read Command in number of cycles. Number of cycles is
between 0 and 15. This field is used for SDR-SDRAM and DDR-SDRAM devices. In the case of SDR-SDRAM devices and
Low-power DDR-SDRAM, this field is equivalent to TXSR timing.
• TXSRD: ExiT Self Refresh Delay to Read Command
Reset Value is C8.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 255 cycles.This field is unique to DDR-SDRAM devices.
• TXP: Exit Power-down Delay to First Command
Reset Value is 3.
This field defines the delay between cke set high and a Valid Command in number of cycles. Number of cycles is between
0 and 15 cycles. This field is unique to Low-power DDR-SDRAM devices and DDR2-SDRAM devices.
6438F–ATARM–21-Jun-10
31
23
15
–
7
–
DDRSDRC Timing 1 Parameter Register
30
22
14
DDRSDRC_T1PR
Read-write
See
–
6
–
Table 22-9
29
21
13
–
5
–
28
20
12
–
4
TXSRD
TXSNR
“DDRSDRC Write Protect Mode Register” on page
27
19
11
3
TRFC
26
18
10
2
TXP
AT91SAM9G45
25
17
9
1
275.
24
16
8
0
267