AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 601

• Manufacturer Part Number: AT91SAM9G45-CU-999
• Description: IC MCU ARM9 APMC 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

33.7.8.7
Figure 33-42. Synch Field
Figure 33-43. Slave Node Synchronization
6438F–ATARM–21-Jun-10
Fractional Part (FP)
Clcok Divider (CD)
Synchro Counter
US_BRGR
US_BRGR
Baud Rate
LINIDRX
Clock
RXD
Slave Node Synchronization
The synchronization is done only in Slave node configuration. The procedure is based on time
measurement between falling edges of the Synch Field. The falling edges are available in dis-
tances of 2, 4, 6 and 8 bit times.
The time measurement is made by a 19-bit counter clocked by the sampling clock (see
33.7.1).
When the start bit of the Synch Field is detected the counter is reset. Then during the next 8
Tbits of the Synch Field, the counter is incremented. At the end of these 8 Tbits, the counter is
stopped. At this moment, the 16 most significant bits of the counter (value divided by 8) gives the
new clock divider (CD) and the 3 least significant bits of this value (the remainder) gives the new
fractional part (FP).
When the Synch Field has been received, the clock divider (CD) and the fractional part (FP) are
updated in the Baud Rate Generator register (US_BRGR).
The accuracy of the synchronization depends on several parameters:
The following formula is used to compute the deviation of the slave bit rate relative to the master
bit rate after synchronization (F
• The nominal clock frequency (F
• The Baudrate
• The oversampling (Over=0 => 16X or Over=0 => 8X)
13 dominant bits (at 0)
Start
bit
Break Field
2 Tbit
Initial CD
Initial FP
2 Tbit
1 recessive bit
Delimiter
Break
(at 1)
8 Tbit
Synch Field
Reset
SLAVE
2 Tbit
Start
Bit
Nom
1
is the real slave node clock frequency).
) (the theoretical slave node clock frequency)
0
Synch Byte = 0x55
1
2 Tbit
0
1
0
1
0
000_0011_0001_0110_1101
Stop
Bit
Stop
0000_0110_0010_1101
101
bit
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
AT91SAM9G45
Stop
Bit
Section
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