AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 19

IC MCU ARM9 APMC 324TFBGA

AT91SAM9G45-CU-999

Manufacturer Part Number
AT91SAM9G45-CU-999
Description
IC MCU ARM9 APMC 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91SAM9G45-CU-999

Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM9G45-CU-999
Manufacturer:
Atmel
Quantity:
10 000
7. System Controller
6438F–ATARM–21-Jun-10
A[25:0], controlled by 4 registers, DELAY5, DELAY6, DELAY7and DELAY8, located in the
HSMC3 user interface
A25 on PC[12] and A[24:19] on PC[7:2]
The delay can only be inserted on the HSMCI0 and HSMCI1 I/O lines, so on PA[9:2] and
PA[30:23]. The delay is controlled by 2 registers, DELAY1 and DELAY2, located in the PIOA
user interface.
The System Controller is a set of peripherals that allows handling of key elements of the system,
such as power, resets, clocks, time, interrupts, watchdog, etc.
• PIOA User interface
– D[24] <=> DELAY4[3:0],
– D[25] <=> DELAY4[7:4],...,
– D[30] <=> DELAY4[27:24],
– D[31] <=> DELAY4[31:28]
– A[0] <=> DELAY5[3:0],
– A[1] <=> DELAY5[7:4],...,
– A[6] <=> DELAY5[27:24],
– A[7] <=> DELAY5[31:28]
– A[8] <=> DELAY6[3:0],
– A[9] <=> DELAY6[7:4],...,
– A[14] <=> DELAY6[27:24],
– A[15] <=> DELAY6[31:28]
– A[16] <=> DELAY7[3:0],
– A[17] <=> DELAY7[7:4],
– A[18] <=> DELAY7[11:8]
– A19 <=> DELAY7[15:12],
– A20 <=> DELAY7[19:16],...,
– A23 <=> DELAY7[31:28],
– A24 <=> DELAY8[3:0],
– A25 <=> DELAY8[7:4]
– PA[2] <=> DELAY1[3:0],
– PA[3] <=> DELAY1[7:4],...,
– PA[8] <=> DELAY1[27:24],
– PA[9] <=> DELAY1[31:28]
– PA[23] <=> DELAY2[3:0],
– PA[24] <=> DELAY2[7:4],...,
– PA[29] <=> DELAY2[27:24],
– PA[30] <=> DELAY2[31:28]
AT91SAM9G45
19

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