EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 197

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7.4.8 Grayscale/Color Generator for Monochrome/Passive Low Color
Displays
7
The hardware raster engine has three built in matrix programmable grayscale generators.
One generator is located on each of the red, green, and blue internal channels. These
generators can be enabled to expand color depth or turn monochrome into grayscale through
both spatial and temporal dithering. Dithering means that the circuit turns monochrome pixels
on and off in a specific pattern and at a high toggle rate, and uses the integration perception
of the human eye along with display persistence to achieve an average luminance between
full on and full off. Using one of these generators allows creation of grayscale pixels on a
monochrome display. Using all three of the generators with one on each red, green, and blue
channel allows generation of additional colors on an 8 color LCD display.
Grayscale shading is accomplished on each channel by altering when and how often a given
pixel is active. The setup for when and how often pixels of each value 0-7 are active is
programmed into the grayscale look-up-table memory for each channel. The look-up-table for
each RGB channel is indexed by 4 values: 3 bits from the input pixel value (0-7), and for each
input pixel value either the 3 frame or 4 frame counter, the 3 line or 4 line vertical counter, and
the 3 column or 4 column horizontal pixel counter. Pixel values 0-7 in each channel are
programmed as to whether a count by 3 or count by 4 counter is used for frame, horizontal,
and vertical.
The grayscale circuits are inserted into the video pipeline after the color LUT. The circuitry
takes three bits from the output of the color LUT (one from each color) and uses them as the
inputs for the grayscale LUT. These three bits are then processed by the grayscale circuitry to
generate a new three bit output, based on the configuration of the grayscale LUT. The three
bit output of the grayscale LUT is then fed through the pixel shifting logic and out to the Pixel
Bus Pins. This provides 8 shades of gray per channel, including all off (black) and full on
(white). Each circuit operates six separate 2-bit index counters; FRAME_CNT3,
FRAME_CNT4, VERT_CNT3, VERT_CNT4, HORZ_CNT3, and HORZ_CNT4. Based on
value of these counters, each grayscale look-up-table is programmed with values that define
the on/off dithering operation for their respective three bits of the pixel value.
For example, in color mode 8 with shift mode 0:
Color LUT[23:21] -> Grayscale LUT[2] -> P[17:12] (All pins with Red color data)
Color LUT[15:13] -> Grayscale LUT[1] -> P[11:6] (All pins with Green color data)
Color LUT[7:5] -> Grayscale LUT[0] -> P[5:0] (All pins with Blue color data)
The following setup description refers to a single channel. First, the matrix size for each 3 bits
of the pixel value (0 through 7) is defined. The matrix size is from 3 horizontal rows x 3
vertical columns x 3 frames to 4H x 4V x 4F or any combinations of 3 or 4. The grayscale
look-up-table is then filled in for each pixel with this matrix information. Because the look-up-
table is indexed by 4 values, it can be perceived as a multi-dimensional array. For each of the
input pixel values 0-7, a 3H (Horizontal) x 3V (Vertical) x 3F (Frame) cube up to a
4H (Horizontal) x 4V (Vertical) x 4F (Frame) cube can be defined.
Setting the grayscale matrix values in a channel for full off and full on is very straight forward.
DS785UM1
7-15
Copyright 2007 Cirrus Logic