EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 242

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

7
ParllIfOut
7-60
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
31
15
Address: 0x8003_0058
Default: 0x0000_0000
Definition: Parallel Interface Output/Control Register.
Bit Descriptions:
30
14
29
13
RSVD
28
12
This register, if PIFEN = ‘1’ in the
Smart Panel. A Smart Panel has an integrated controller and frame buffer.
RSVD:
RD:
DAT:
P2
1
1
1
1
Table 7-16. Bits per Pixel Scanned Out (Continued)
27
11
P1
0
0
1
1
26
10
Copyright 2007 Cirrus Logic
P0
0
1
0
1
25
9
Reserved - Unknown during read
Read control bit - Write Only
Writing a ‘0’ to this bit location will initiate a parallel
interface write cycle; writing a ‘1’ will initiate a parallel
interface read cycle:
1 - Start Smart Panel write cycle
0 - Start Smart Panel read cycle
Data - Write Only
The value written to this field is output on the parallel
interface pins during a write cycle. Writing PIFEN = ‘1’ to
the
pins for Parallel Interface (Smart Panel) operation:
V_CSYNC --> D7 (Smart Panel)
HSYNC --> D6
BLANK --> D5
P17 --> D4
VideoAttribs
RD
24
8
32 bits per pixel (24 bits per pixel unpacked)
RSVD
23
7
24 bits per pixel packed
16 bits per pixel
VideoAttribs
Pixel Mode
do not use
register redefines the signals on these
22
6
21
5
register, is used to access a
20
4
DAT
19
3
18
2
17
1
DS785UM1
16
0