EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 49

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

DS785UM1
2.2.8.2 SDRAM Slave Arbiter
2.2.8.3 EBI Bus Arbiter
2.3.1 AHB Slave
2.3 AHB Decoder
The SDRAM Slave Arbiter prioritizes between accesses from the AHB bus and the Raster
DMA bus. If an access request from the AHB arrives at the same time as an access request
from the Raster DMA, the Raster DMA will be given access while the AHB request is queued.
The EBI Bus Arbiter is used to arbitrate between accesses from the SDRAM controller and
the Static Memory controller, where priority is given to accesses from the SDRAM controller.
The AHB Decoder contains the device memory map for all of the AHB masters/slaves and for
the APB bridge. When a particular address range is selected, the appropriate signal is
generated as defined in
(For additional information, see 17,
An AHB Slave responds to transfers initiated by bus masters. The slave uses signals from
the decoder to determine when it should respond to a bus transfer. All other signals required
for the transfer, such as the address and control information, are generated by the bus
master.
Note: Due to decoding optimization, the AHB peripheral registers are aliased throughout each
peripherals register bank. Do not attempt to access an unspecified register within the
bank.
0x800C_0000 - 0x800C_FFFF
0x800D_0000 - 0x800F_FFFF
0x800B_0000 - 0x800B_FFFF
0x800A_0000 - 0x800A_FFFF
0x8009_0000 - 0x8009_FFFF
0x8008_0000 - 0x8008_FFFF
0x8007_0000 - 0x8007_FFFF
0x8006_0000 - 0x8006_FFFF
0x8005_0000 - 0x8005_FFFF
0x8004_0000 - 0x8004_FFFF
0x8003_0000 - 0x8003_FFFF
0x8002_0000 - 0x8002_FFFF
0x8001_0000 - 0x8001_FFFF
0x8000_0000 - 0x8000_FFFF
Address Range
Table
Table 2-2. AHB Peripheral Address Range
Copyright 2007 Cirrus Logic
2-2.
Register Width
“Reference Documents” on page
32
32
32
32
32
32
32
32
32
32
-
-
-
-
ARM920T Core and Advanced High-Speed Bus (AHB)
Peripheral Type
AHB
AHB
AHB
AHB
AHB
AHB
AHB
AHB
AHB
AHB
-
-
-
-
Reserved
VIC2
VIC1
IDE
Boot ROM physical address
SRAM Controller/ PCMCIA
Reserved
SDRAM Controller
Reserved
Reserved
Raster
USB Host
Ethernet MAC
DMA
Peripheral
EP93xx User’s Guide
P-3.
2-11
2