EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 273

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

DS785UM1
8.5.1.2 Example: 24 BPP (packed) mode
8.5.2 Pixel End and Start
If a Block Copy starts at pixel 3 and 10 pixels are to be copied, the
would be loaded with 0x3 (4 words - 1 word = 0x3). The pixels fetched are highlighted in
Table
If a Block Copy starts at pixel 0 and copies 5 pixels, the
filled with 0x3. This is because the first four pixels consume 3 words and the 5th pixel
consumes part of 1 word. This is a total of 4 words. So, the word width is 4 words - 1 word =
0x3. The pixels fetched are highlighted in
If a Block Copy starts at pixel 2 and copies 6 pixels, the
filled with 0x4. This is because the 1st pixel consumes part of the 1st word and the 4
remaining pixels consume the next 4 words. So, the word width is 5 words - 1 word = 0x4.
The pixels fetched are highlighted in
Two registers are used to control where in a word the first and last pixels reside. This is
required since in all color depths more than 1 pixel can reside in a word of memory. This fact
requires that the programmer provide the hardware with the exact information of where in a
32-bit word a pixel starts or ends. One register, “SRCPIXELSTRT”, is used for the source
0x0000 -
0x0000 -
0x0000 -
0x0000 -
0x0010 -
Address
Address
Address
Address
0x000C
0x000C
0x000C
0x000C
0x001C
8-10.
31
31
31
31
AA
FF
FF
55
55
EE
EE
AA
44
44
DD
DD
44
44
99
CC
CC
44
44
99
Table 8-10. Transfer Example 3
Table 8-11. Transfer Example 4
Table 8-12. Transfer Example 5
Table 8-9. Transfer Example 2
0 31
0 31
0 31
0 31
Copyright 2007 Cirrus Logic
BB
BB
33
33
99
Table
AA
AA
33
33
88
Table
99
99
33
33
88
8-12.
88
88
22
22
88
0 31
0 31
0 31
0 31
8-11.
77
77
22
22
77
66
66
22
22
77
“BLKSRCWIDTH”
“BLKSRCWIDTH”
55
55
11
11
77
44
44
11
11
66
0 31
0 31
0 31
0 31
“BLKSRCWIDTH”
33
33
11
11
66
22
22
00
00
66
Graphics Accelerator
EP93xx User’s Guide
register would be
00
register would be
00
55
11
11
00
00
00
00
55
0
0
0
0
register
8-9
8