EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 581

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

UART3LinCtrlHigh
DS785UM1
31
15
Address:
Default:
Definition:
30
14
29
13
28
12
BE:
PE:
FE:
0x808E_0008 - Read/Write
0x0000_0000
UART3 Line Control Register High. UART3LinCtrlHigh, UART3LinCtrlMid and
UART3LinCtrlLow form a single 23-bit wide register (UART3LinCtrl) which is
updated on a single write strobe generated by an UART3LinCtrlHigh write. So,
in order to internally update the contents of UART3LinCtrlMid or
UARTBLCR_L, a UART3LinCtrlHigh write must always be performed at the
end.
To update the three registers there are two possible sequences:
• UART3LinCtrlLow write, UART3LinCtrlMid write and UART3LinCtrlHigh write
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Break Error. This bit is set to 1 if a break condition was
detected, indicating that the received data input was held
LOW for longer than a full-word transmission time (defined
as start, data, parity and stop bits). This bit is cleared to 0
after a write to UART3RXSts. In FIFO mode, this error is
associated with the character at the top of the FIFO. When
a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive
data input goes to a 1 (marking state) and the next valid
start bit is received.
Parity Error. When this bit is set to 1, it indicates that the
parity of the received data character does not match the
parity selected in UART3LinCtrlHigh (bit 2). This bit is
cleared to 0 by a write to UART3RXSts. In FIFO mode,
this error is associated with the character at the top of the
FIFO.
Framing Error. When this bit is set to 1, it indicates that the
received character did not have a valid stop bit (a valid
stop bit is 1). This bit is cleared to 0 by a write to
UART3RXSts. In FIFO mode, this error is associated with
the character at the top of the FIFO.
24
8
RSVD
23
7
22
6
WLEN
21
5
FEN
20
4
UART3 With HDLC Encoder
STP2
19
3
EP93xx User’s Guide
EPS
18
2
PEN
17
1
BRK
16
16-5
0
16