DF36912GFH Renesas Electronics America, DF36912GFH Datasheet - Page 267

MCU 3/5V 8K 32-LQFP

DF36912GFH

Manufacturer Part Number
DF36912GFH
Description
MCU 3/5V 8K 32-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of DF36912GFH

Core Processor
H8/300H
Core Size
16-Bit
Speed
12MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF36912GFH
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
DF36912GFHV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
14.8.4
In asynchronous mode, SCI3 operates on a basic clock with a frequency of 16 times the transfer
rate. In reception, SCI3 samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the
basic clock as shown in figure 14.20. Thus, the reception margin in asynchronous mode is given
by formula (1) below.
Legend N : Ratio of bit rate to clock (N = 16)
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
M = (0.5 –
D : Clock duty (D = 0.5 to 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
M = {0.5 – 1/(2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
Internal basic
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 14.20 Receive Data Sampling Timing in Asynchronous Mode
2N
1
) –
16)}
0
D – 0.5
8 clocks
Start bit
N
100 [%] = 46.875%
16 clocks
– (L – 0.5) F
7
Section 14 Serial Communication Interface 3 (SCI3)
100(%)
15 0
Rev. 3.00 Sep. 14, 2006 Page 237 of 408
D0
7
... Formula (1)
REJ09B0105-0300
15 0
D1

Related parts for DF36912GFH