DF36912GFH Renesas Electronics America, DF36912GFH Datasheet - Page 281

MCU 3/5V 8K 32-LQFP

DF36912GFH

Manufacturer Part Number
DF36912GFH
Description
MCU 3/5V 8K 32-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of DF36912GFH

Core Processor
H8/300H
Core Size
16-Bit
Speed
12MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF36912GFH
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
DF36912GFHV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit Bit Name
4
3
2
NACKF
STOP
AL/OVE
0
0
0
Initial Value R/W Description
R/W No Acknowledge Detection Flag
R/W Stop Condition Detection Flag
R/W Arbitration Lost Flag/Overrun Error Flag
[Setting condition]
[Clearing condition]
[Setting conditions]
[Clearing condition]
This flag indicates that arbitration was lost in master mode
with the I
received while RDRF = 1 with the clocked synchronous
format.
When two or more master devices attempt to seize the bus
at nearly the same time, if the I
differing from the data it sent, it sets AL to 1 to indicate that
the bus has been taken by another master.
[Setting conditions]
[Clearing condition]
When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER is 1
When 0 is written in NACKF after reading NACKF = 1
In master mode, when a stop condition is detected after
frame transfer
In slave mode, when a stop condition is detected
after the general call address or the first byte slave
address, next to detection of start condition, accords
with the address set in SAR
When 0 is written in STOP after reading STOP = 1
If the internal SDA and SDA pin disagree at the rise of
SCL in master transmit mode
When the SDA pin outputs high in master mode while a
start condition is detected
When the final bit is received with the clocked
synchronous format while RDRF = 1
When 0 is written in AL/OVE after reading AL/OVE=1
2
C bus format and that the final bit has been
Rev. 3.00 Sep. 14, 2006 Page 251 of 408
Section 15 I
2
C bus interface detects data
2
C Bus Interface 2 (IIC2)
REJ09B0105-0300

Related parts for DF36912GFH