DF36912GFH Renesas Electronics America, DF36912GFH Datasheet - Page 278

MCU 3/5V 8K 32-LQFP

DF36912GFH

Manufacturer Part Number
DF36912GFH
Description
MCU 3/5V 8K 32-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of DF36912GFH

Core Processor
H8/300H
Core Size
16-Bit
Speed
12MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF36912GFH
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
DF36912GFHV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 15 I
15.3.4
ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be
transferred, and confirms acknowledge bits to be received.
Rev. 3.00 Sep. 14, 2006 Page 248 of 408
REJ09B0105-0300
Bit Bit Name
7
6
5
TIE
TEIE
RIE
I
2
2
C Bus Interrupt Enable Register (ICIER)
C Bus Interface 2 (IIC2)
Initial Value R/W Description
0
0
0
R/W Transmit Interrupt Enable
R/W Transmit End Interrupt Enable
R/W Receive Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables or
disables the transmit data empty interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is disabled.
1: Transmit data empty interrupt request (TXI) is enabled.
This bit enables or disables the transmit end interrupt (TEI) at
the rising of the ninth clock while the TDRE bit in ICSR is 1.
TEI can be canceled by clearing the TEND bit or the TEIE bit
to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
This bit enables or disables the receive data full interrupt
request (RXI) and the overrun error interrupt request (ERI)
with the clocked synchronous format, when a receive data is
transferred from ICDRS to ICDRR and the RDRF bit in ICSR
is set to 1. RXI can be canceled by clearing the RDRF or RIE
bit to 0.
0: Receive data full interrupt request (RXI) and overrun error
1: Receive data full interrupt request (RXI) and overrun error
interrupt request (ERI) with the clocked synchronous
format are disabled.
interrupt request (ERI) with the clocked synchronous
format are enabled.

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