DF36912GFH Renesas Electronics America, DF36912GFH Datasheet - Page 96

• Manufacturer Part Number: DF36912GFH
• Description: MCU 3/5V 8K 32-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36912GFH

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 12MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Address Break
4.1.2
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
4.1.3
BARH and BARL are 16-bit read/write registers that set the address for generating an address
break interrupt. When setting the address break condition to the instruction execution cycle, set the
first byte address of the instruction. The initial value of this register is H'FFFF.
4.1.4
BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break
interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8-
bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for
even and odd addresses in the data transmission. Therefore, comparison data must be set in BDRH
for byte access. For word access, the data bus used depends on the address. See section 4.1.1,
Address Break Control Register (ABRKCR), for details. The initial value of this register is
undefined.
Rev. 3.00 Sep. 14, 2006 Page 66 of 408
REJ09B0105-0300
Bit
7
6
5 to 0
Bit Name
ABIF
ABIE
—
Address Break Status Register (ABRKSR)
Break Address Registers (BARH, BARL)
Break Data Registers (BDRH, BDRL)
Initial
Value
0
0
All 1
R/W
R/W
R/W
—
Description
Address Break Interrupt Flag
[Setting condition]
[Clearing condition]
Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
Reserved
These bits are always read as 1.
When the condition set in ABRKCR is satisfied
When 0 is written after ABIF=1 is read