R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 1090

• Manufacturer Part Number: R4F24269NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24269NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 Synchronous Serial Communication Unit (SSU)
Page 1060 of 1372
[1]
[2]
[3]
[4]
Note: Hatching boxes represent SSU internal operations.
Data transferred from SSTDR to SSTRSR
Set TDRE to 1 to start transmission
Confirm that TEND is cleared to 0
Write transmit data to SSTDR
TDRE automatically cleared
Consecutive data transmission?
Clear TE in SSER to 0
Read TDRE in SSSR
Read TEND in SSSR
quantum elapsed?
End transmission
Figure 19.6 Flowchart Example of Data Transmission (SSU Mode)
Clear TEND to 0
Initial setting
One bit time
TDRE = 1?
TEND = 1?
Yes
Yes
Yes
No
Start
Yes
No
No
No
[1] Initial setting:
[2] Check that the SSU state and write transmit data:
[3] Procedure for consecutive data transmission:
[4] Procedure for data transmission end:
Specify the transmit data format.
Write transmit data to SSTDR after reading and confirming
that the TDRE bit is 1. The TDRE bit is automatically cleared
to 0 and transmission is started by writing data to SSTDR.
To continue data transmission, confirm that the TDRE bit is 1
meaning that SSTDR is ready to be written to. After that, data
can be written to SSTDR. The TDRE bit is automatically
cleared to 0 by writing data to SSTDR.
To end data transmission, confirm that the TEND bit is cleared
to 0. After completion of transmitting the last bit, clear the TE
bit to 0.
H8S/2426, H8S/2426R, H8S/2424 Group
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010