R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 1185

• Manufacturer Part Number: R4F24269NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24269NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
23.2.3
(1)
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby
mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop.
However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip
peripheral functions other than the SCI, IIC, and SSU, and the states of I/O ports, are retained.
Whether the address bus and bus control signals are placed in the high-impedance state or retain
the output state can be specified by the OPE bit in SBYCR.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
(2)
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ15*), or
by means of the RES pin or STBY pin. Setting the SSI bit in SSIER to 1 enables IRQ0 to IRQ15*
to be used as software standby mode clearing sources.
• Clearing with an Interrupt:
Note: * IRQ8 to IRQ15 are not supported by the H8S/2424 group.
• Clearing with the RES Pin:
• Clearing with the STBY Pin:
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
When an NMI or IRQ0 to IRQ15* interrupt request signal is input, clock oscillation starts, and
stable clocks are supplied to the entire LSI after the elapse of the time set in bits STS3 to STS0
in SBYCR. Then, software standby mode is cleared, and interrupt exception handling is
started.
When clearing software standby mode with an IRQ0 to IRQ15* interrupt, set the
corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts
IRQ0 to IRQ15* is generated. Software standby mode cannot be cleared if the interrupt has
been masked on the CPU side or has been designated as a DTC activation source.
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low
until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception
handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Transition to Software Standby Mode
Clearing Software Standby Mode
Software Standby Mode
Section 23 Power-Down Modes
Page 1155 of 1372