R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 1097

• Manufacturer Part Number: R4F24269NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24269NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
19.4.6
When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is
cleared to 0, the SCS pin functions as an input (Hi-Z) to detect conflict error. The conflict
detection period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after
transfer ends. When a low level signal is input to the SCS pin within the period, a conflict error
occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0.
Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
before resuming the transmission or reception.
External input to SCS
Internal-clocked SCS
MSS
Internal signal for
transfer enable
CE
SCS output
φ
SCS
MSS
Internal signal for
transfer enable
CE
SCS Pin Control and Conflict Error
Figure 19.11 Conflict Error Detection Timing (After Transfer End)
Figure 19.10 Conflict Error Detection Timing (Before Transfer)
(Hi-Z)
Transfer
end
detection period
Conflict error
Data written
to SSTDR
internally clocking SCS
Maximum time for
Section 19 Synchronous Serial Communication Unit (SSU)
Conflict error detection period
(Hi-Z)
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