R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 219

• Manufacturer Part Number: R4F24269NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24269NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
6.4.3
The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of
ROM, SRAM, and so on; an address/data multiplexed I/O interface that allows direct connection
of peripheral LSIs that require address/data multiplexing, a DRAM interface that allows direct
connection of DRAM; a synchronous DRAM interface that allows direct connection of
synchronous DRAM; and a burst ROM interface that allows direct connection of burst ROM. The
interface can be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space. An area for
which the address/data multiplexed I/O interface is designated functions as address/data
multiplexed I/O space, an area for which the DRAM interface is designated functions as DRAM
space, an area for which the synchronous DRAM interface is designated functions as continuous
synchronous DRAM space, and an area for which the burst ROM interface is designated functions
as burst ROM space.
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode.
Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424
(1)
Area 0 includes on-chip ROM in expanded mode with on-chip ROM enabled and the space
excluding on-chip ROM is external address space, and in expanded mode with on-chip ROM
disabled, all of area 0 is external address space.
When area 0 external space is accessed, the CS0 signal can be output.
Either the basic bus interface or burst ROM interface can be selected for the memory interface of
area 0.
(2)
In externally expanded mode, all of area 1 is external address space.
When area 1 external address space is accessed, the CS1 signal can be output.
Either the basic bus interface or burst ROM interface can be selected for the memory interface of
area 1.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Area 0
Area 1
Group. The DRAM interface is not supported by the 5-V version.
Memory Interfaces
Section 6 Bus Controller (BSC)
Page 189 of 1372