R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 441

• Manufacturer Part Number: R4F24269NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24269NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
8.3.2
EDDAR is a 32-bit readable/writable register that specifies the transfer destination address. An
address update function is provided that updates the register contents to the next transfer
destination address each time transfer processing is performed. In single address mode, the
EDDAR value is ignored when a device with DACK is specified as the transfer destination.
The upper 8 bits of EDDAR are reserved; they are always read as 0 and cannot be modified. Only
0 should be written to these bits.
EDDAR can be read at all times by the CPU. When reading EDDAR for a channel on which
EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write
to EDDAR for a channel on which EXDMA transfer is in progress. The initial values of EDDAR
are undefined.
8.3.3
EDTCR specifies the number of transfers. The function differs according to the transfer mode. Do
not write to EDTCR for a channel on which EXDMA transfer is in progress.
(1)
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Bit
31 to 24
23 to 0
Normal Transfer Mode
EXDMA Destination Address Register (EDDAR)
EXDMA Transfer Count Register (EDTCR)
Bit Name
⎯
Initial Value
All 0
All 0
R/W
⎯
R/W
Description
Reserved
These bits are always read as 0 and cannot be
modified.
24-Bit Transfer Counter
These bits specify the number of transfers. Setting
H'000001 specifies one transfer. Setting H'000000
means no specification for the number of
transfers, and the transfer counter function is
halted. In this case, there is no transfer end
interrupt by the transfer counter. Setting
H'FFFFFF specifies the maximum number of
transfers, that is 16,777,215. During EXDMA
transfer, this counter shows the remaining number
of transfers.
This counter can be read at all times. When
reading EDTCR for a channel on which EXDMA
transfer processing is in progress, a longword-size
read must be executed.
Section 8 EXDMA Controller (EXDMAC)
Page 411 of 1372