HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 17

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11.2 Register Descriptions ........................................................................................................ 439
11.3 Operation .......................................................................................................................... 452
11.4 Usage Notes ...................................................................................................................... 459
Section 12 Watchdog Timer
12.1 Overview........................................................................................................................... 461
12.2 Register Descriptions ........................................................................................................ 464
12.3 Operation .......................................................................................................................... 471
12.4 Interrupts ........................................................................................................................... 475
12.5 Usage Notes ...................................................................................................................... 475
11.2.1 Port A Data Direction Register (PADDR) ........................................................... 439
11.2.2 Port A Data Register (PADR) .............................................................................. 439
11.2.3 Port B Data Direction Register (PBDDR)............................................................ 440
11.2.4 Port B Data Register (PBDR) .............................................................................. 440
11.2.5 Next Data Register A (NDRA) ............................................................................ 441
11.2.6 Next Data Register B (NDRB)............................................................................. 443
11.2.7 Next Data Enable Register A (NDERA).............................................................. 445
11.2.8 Next Data Enable Register B (NDERB) .............................................................. 446
11.2.9 TPC Output Control Register (TPCR) ................................................................. 447
11.2.10 TPC Output Mode Register (TPMR) ................................................................... 450
11.3.1 Overview.............................................................................................................. 452
11.3.2 Output Timing...................................................................................................... 453
11.3.3 Normal TPC Output............................................................................................. 454
11.3.4 Non-Overlapping TPC Output ............................................................................. 456
11.3.5 TPC Output Triggering by Input Capture ............................................................ 458
11.4.1 Operation of TPC Output Pins ............................................................................. 459
11.4.2 Note on Non-Overlapping Output........................................................................ 459
12.1.1 Features................................................................................................................ 461
12.1.2 Block Diagram ..................................................................................................... 462
12.1.3 Pin Configuration................................................................................................. 462
12.1.4 Register Configuration......................................................................................... 463
12.2.1 Timer Counter (TCNT)........................................................................................ 464
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 465
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 467
12.2.4 Notes on Register Access..................................................................................... 469
12.3.1 Watchdog Timer Operation ................................................................................. 471
12.3.2 Interval Timer Operation ..................................................................................... 472
12.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 473
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 474
............................................................................................. 461
Rev. 4.00 Jan 26, 2006 page xv of xxii