HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 235

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.1.3
Table 7.1 gives an overview of the DMAC functions.
Table 7.1
Transfer Mode
Short
address
mode
Full
address
mode
I/O mode
Idle mode
Repeat mode
Normal mode
Block transfer
Functional Overview
Transfers one byte or one word
per request
Increments or decrements the memory
address by 1 or 2
Executes 1 to 65,536 transfers
Transfers one byte or one word per
request
Holds the memory address fixed
Executes 1 to 65,536 transfers
Transfers one byte or one word per
request
Increments or decrements the memory
address by 1 or 2
Executes a specified number (1 to 255)
of transfers, then returns to the initial
state and continues
Auto-request
External request
Transfers one block of a specified size
per request
Executes 1 to 65,536 transfers
Allows either the source or destination to
be a fixed block area
Block size can be 1 to 255 bytes or
words
DMAC Functional Overview
Retains the transfer request
internally
Executes a specified number(1 to
65,536) of transfers continuously
Selection of burst mode or cycle-
steal mode
Transfers one byte or one word per
request
Executes 1 to 65,536 transfers
Activation
Compare match/input
capture A interrupts from
16-bit timer channels 0 to
2
Transmit-data-empty
interrupt from SCI channel
0
Conversion-end interrupt
from A/D converter
Receive-data-full interrupt
from SCI channel 0
External request
Auto-request
External request
Compare match/ input
capture A interrupts from
16-bit timer channels 0 to
2
External request
Conversion-end interrupt
from A/D converter
Rev. 4.00 Jan 26, 2006 page 211 of 938
Section 7 DMA Controller
Address Reg. Length
Source Destination
24
8
24
24
24
REJ09B0276-0400
8
24
8
24
24