HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 388
HD64F3067RF20
Manufacturer Part Number
HD64F3067RF20
Description
IC H8 MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.DF3067RF20VTR.pdf
(965 pages)
Specifications of HD64F3067RF20
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Package
100PQFP
Family Name
H8
Maximum Speed
20 MHz
Operating Supply Voltage
5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
70
Interface Type
SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 9 16-Bit Timer
2. For periodic counting, set CCLR1 and CCLR0 in TCR to have TCNT cleared at GRA compare
3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected in
4. Write the count period in GRA or GRB, whichever was selected in step 2.
5. Set the STR bit to 1 in TSTR to start the timer counter.
When a channel is set to have its counter cleared by compare match, in that channel TCNT
operates as a periodic counter. Select the output compare function of GRA or GRB, set bit CCLR1
or CCLR0 in TCR to have the counter cleared by compare match, and set the count period in GRA
or GRB. After these settings, the counter starts counting up as a periodic counter when the
corresponding bit is set to 1 in TSTR. When the count matches GRA or GRB, the IMFA or IMFB
flag is set to 1 in TISRA/TISRB and the counter is cleared to H'0000. If the corresponding IMIEA
or IMIEB bit is set to 1 in TISRA/TISRB, a CPU interrupt is requested at this time. After the
compare match, TCNT continues counting up from H'0000. Figure 9.14 illustrates periodic
counting.
Rev. 4.00 Jan 26, 2006 page 364 of 938
REJ09B0276-0400
match or GRB compare match.
step 2.
Free-running and periodic counter operation
A reset leaves the counters (TCNTs) in 16-bit timer channels 0 to 2 all set as free-running
counters. A free-running counter starts counting up when the corresponding bit in TSTR is set
to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC.
After the overflow, the counter continues counting up from H'0000. Figure 9.13 illustrates
free-running counting.
H'FFFF
H'0000
STR0 to
STR2 bit
OVF
TCNT value
Figure 9.13 Free-Running Counter Operation
Time
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