HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 659

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

18.5.3
Flash memory erasing should be performed block by block following the procedure shown in the
erase/erase-verify flowchart (single-block erase) shown in figure 18.12.
For the wait time (x, y, z, , , , , ) after setting or clearing of each bit in the flash memory
control register (FLMCR and the maximum erase count (N)), see table 21.19 of section 21.2.6,
Flash Memory Characteristics.
To erase the contents of flash memory, make a 1 bit setting for the flash memory area to be erased
in erase block register (EBR) at least (x) µs after setting the SWE bit to 1 in FLMCR. Next, the
watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set a value
greater than ( z ) ms + (y +
mode (erase setup) is performed next by setting the ESU bit in FLMCR. The operating mode is
then switched to erase mode by setting the E bit in FLMCR after the elapse of at least (y) µs.
The time during which the E bit is set is the flash memory erase time. Ensure that the erase time
does not exceed (z) ms.
Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased
18.5.4
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the fixed erase time, clear the E bit in FLMCR, then wait for at least ( ) µs
before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer
setting is also cleared. The operating mode is then switched to erase-verify mode by setting the EV
bit in FLMCR. Before reading in erase-verify mode, a dummy write of H'FF data should be made
to the addresses to be read. The dummy write should be executed after the elapse of ( ) µs or more.
When the flash memory is read in this state (verify data is read in 16-bit units), the data at the
latched address is read. Wait at least ( ) µs after the dummy write before performing this read
operation. If the read data has been erased (all “1”), a dummy write is performed to the next
address, and erase-verify is performed. If the read data is unerased, set erase mode again, and
repeat the erase/erase-verify sequence as before. However, do not repeat the erase/erase-verify
sequence more than (N) times.
to “0”) is not necessary before starting the erase procedure.
Erase Mode
Erase-Verify Mode
+ ß) µs as the WDT overflow period. Preparation for entering erase
Rev. 4.00 Jan 26, 2006 page 635 of 938
REJ09B0276-0400
Section 18 ROM