HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 464

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 11 Programmable Timing Pattern Controller (TPC)
11.2.3
PBDDR is an 8-bit write-only register that selects input or output for each pin in port B.
Port B is multiplexed with pins TP
be set to 1. For further information about PBDDR, see section 8.12, Port B.
11.2.4
PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when
these TPC output groups are used.
For further information about PBDR, see section 8.12, Port B.
Rev. 4.00 Jan 26, 2006 page 440 of 938
REJ09B0276-0400
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Note: * Bits selected for TPC output by NDERB settings become read-only bits.
Port B Data Direction Register (PBDDR)
Port B Data Register (PBDR)
PB
R/(W)*
PB
7
W
0
7
0
7
DDR
7
PB
R/(W)*
PB
6
W
0
6
0
6
DDR
6
15
to TP
PB
R/(W)*
PB
5
W
0
5
0
5
DDR
8
. Bits corresponding to pins used for TPC output must
5
Port B direction 7 to 0
These bits select input or
output for port B pins
Port B data 7 to 0
These bits store output data
for TPC output groups 2 and 3
PB
R/(W)*
PB
4
W
0
4
0
4
DDR
4
PB
R/(W)*
PB
3
W
0
3
0
3
DDR
3
PB
R/(W)*
PB
2
W
0
2
0
2
DDR
2
PB
R/(W)*
PB
1
W
0
1
0
1
DDR
1
PB
R/(W)*
PB
0
W
0
0
0
0
DDR
0