HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 146

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Section 2 Instruction Descriptions
2.2.37
LDMAC (LoaD to MAC register)
Operation
ERs
or
ERs
Assembly-Language Format
LDMAC ERs, MAC register
Operand Size
Longword
Description
This instruction moves the contents of a general register to a multiply-accumulate register (MACH
or MACL). If the transfer is to MACH, only the lowest 10 bits of the general register are
transferred.
Supported only by the H8S/2600 CPU.
Available Registers
ERs: ER0 to ER7
Operand Format and Number of States Required for Execution
Note: * A maximum of three additional states are required for execution of this instruction within three states
Notes
Execution of this instruction clears the overflow flag in the multiplier to 0.
Rev. 4.00 Feb 24, 2006 page 130 of 322
REJ09B0139-0400
Register direct
Register direct
Addressing
Mode
MACH
MACL
after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP)
between the MAC instruction and this instruction, this instruction will be two states longer.
The number of states may differ depending on the product. For details, refer to the relevant
microcontroller hardware manual of the product in question.
LDMAC
Mnemonic
LDMAC
LDMAC
ERs, MACH
ERs, MACL
Operands
1st byte
0
0
3
3
Condition Code
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
2nd byte
2
3
Instruction Format
I
0 ers
0 ers
UI H
3rd byte
U
N
Load MAC Register
4th byte
Z
— —
V
States
No. of
C
2*
2*

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