HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 146
Manufacturer Part Number
IC H8S MCU FLASH 256K 128-QFP
Renesas Electronics America
Specifications of HD64F2638F20J
CAN, SCI, SmartCard
Motor Control PWM, POR, PWM, WDT
Number Of I /o
Program Memory Size
256KB (256K x 8)
Program Memory Type
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
A/D 12x10b; D/A 2x8b
-40°C ~ 85°C
Package / Case
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Section 2 Instruction Descriptions
LDMAC (LoaD to MAC register)
LDMAC ERs, MAC register
This instruction moves the contents of a general register to a multiply-accumulate register (MACH
or MACL). If the transfer is to MACH, only the lowest 10 bits of the general register are
Supported only by the H8S/2600 CPU.
ERs: ER0 to ER7
Operand Format and Number of States Required for Execution
Note: * A maximum of three additional states are required for execution of this instruction within three states
Execution of this instruction clears the overflow flag in the multiplier to 0.
Rev. 4.00 Feb 24, 2006 page 130 of 322
after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP)
between the MAC instruction and this instruction, this instruction will be two states longer.
The number of states may differ depending on the product. For details, refer to the relevant
microcontroller hardware manual of the product in question.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Load MAC Register