IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part NumberHD64F2638F20J
DescriptionIC H8S MCU FLASH 256K 128-QFP
ManufacturerRenesas Electronics America
SeriesH8® H8S/2600
HD64F2638F20J datasheets
 


Specifications of HD64F2638F20J

Core ProcessorH8S/2600Core Size16-Bit
Speed20MHzConnectivityCAN, SCI, SmartCard
PeripheralsMotor Control PWM, POR, PWM, WDTNumber Of I /o72
Program Memory Size256KB (256K x 8)Program Memory TypeFLASH
Ram Size16K x 8Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 V
Data ConvertersA/D 12x10b; D/A 2x8bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case128-QFP
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantEeprom Size-
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The revision list can be viewed directly by clicking the title page.
The revision list summarizes the locations of revisions and additions.
Details should always be checked by referring to the relevant text.
H8S/2639, H8S/2638, H8S/2636,
16
H8S/2630, H8S/2635 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2600 Series
Rev.8.00 2010.05

HD64F2638F20J Summary of contents

  • Page 1

    The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2639, H8S/2638, H8S/2636, 16 H8S/2630, H8S/2635 Group ...

  • Page 2

    All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

  • Page 3

    General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...

  • Page 4

    Page REJ09B0103-0800 Rev. 8.00 May 28, 2010 ...

  • Page 5

    This LSI has the internal 32-bit H8S/2600 CPU and includes a variety of peripheral functions necessary for a system configuration. It serves as a high-performance microcomputer. The on-chip peripheral devices include a 16-bit timer pulse unit (TPU), a programmable pulse ...

  • Page 6

    Related manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635 Group Manuals: Document Title H8S/2636, H8S/2638, H8S/2639, ...

  • Page 7

    Main Revisions in This Edition Item Page 1.3.1 Pin Arrangement 10 Figure 1-3 Pin Arrangement of H8S/2638 Group and H8S/2630 Group (FP-128B: Top View) 1.4 Differences Table amended between H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635, and H8S/2634 Table ...

  • Page 8

    Item Page 2.6.3 Table of 50 Instructions Classified by Function Table 2-3 Instructions Classified by Function 2.8.1 Overview 63 Figure 2-14 Processing States 2.8.3 Exception- 65 Handling State 3.4 Pin Functions in 86 Each Operating Mode Table 3-3 Pin Functions ...

  • Page 9

    Item Page 4.7 Notes on Use of 103 the Stack Figure 4-6 Operation when SP Value Is Odd 5.4.3 Interrupt Control 127 Mode 2 Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 9.8.3 Pin ...

  • Page 10

    Item Page 9.8.3 Pin Functions for 279 Each Mode Figure 9-13 Port C Pin Functions (Mode 6) Figure 9-14 Port C Pin 280 Functions (Mode 7) 10.6.2 Interrupt Signal 387 Timing Status Flag Clearing Timing: 10.7 Usage Notes 397 Interrupts ...

  • Page 11

    Item Page 13.5 Usage Notes 507 Restrictions on Use of DTC* Operation in Case of Mode Transition • Transmission 14.1.1 Features 513 14.2.2 Serial Status 520 Register (SSR) 14.3.6 Data Transfer 533 Operations Serial Data Transmission (Except Block Transfer Mode): ...

  • Page 12

    Item Page 14.4 Usage Notes 544 Retransfer Operations (Except Block Transfer Mode): • Retransfer operation when SCI is transmit mode 15.2.9 Module Stop 575 Control Register B (MSTPCRB) 15.3.6 Slave Transmit 594 Operation Figure 15-18 Example of Slave Transmit Mode ...

  • Page 13

    Item Page 16.2.6 Transmit Wait 626 Cancel Register (TXCR) 16.2.7 Transmit 627 Acknowledge Register (TXACK) 16.2.8 Abort 628 Acknowledge Register (ABACK) 16.2.16 Unread 641 Message Status Register (UMSR) 16.2.17 Local 643 Acceptance Filter Masks (LAFML, LAFMH) LAFMH Bits 7 to ...

  • Page 14

    Item Page 16.2.20 Module Stop 650 Control Register C (MSTPCRC) Bit 2—Module Stop (MSTPC2)*: 16.3.2 Initialization 655 after Hardware Reset Table 16-3 BCR Register Value Setting Ranges Table 16-4 Setting 657 Range for TSEG1 and TSEG2 in BCR 16.3.8 DTC ...

  • Page 15

    Item Page 21A.4.3 Mode 749 Transitions Figure 21A-3 Flash Memory State Transitions 21A.5 Pin 755 Configuration Table 21A-5 Pin Configuration 21A.9.2 Program- 777 Verify Mode Figure 21A-12 Program/Program- Verify Flowchart 21A.9.3 Erase Mode 778 REJ09B0103-0800 Rev. 8.00 May 28, 2010 ...

  • Page 16

    Item Page 21A.9.4 Erase-Verify 780 Mode Figure 21A-13 Erase/Erase-Verify Flowchart 21A.13 Programmer 787 Mode 21B.4.3 Mode 801 Transitions Figure 21B-3 Flash Memory State Transitions 21B.7.6 Flash Memory 816 Power Control Register (FLPWCR) Page xvi of l Revision (See Manual for ...

  • Page 17

    Item Page 21B.9.1 Program Mode 826 21B.9.2 Program- 830 Verify Mode Figure 21B-12 Program/Program- Verify Flowchart 21B.9.3 Erase Mode 831 REJ09B0103-0800 Rev. 8.00 May 28, 2010 Revision (See Manual for Details) Description amended The wait times after bits are set ...

  • Page 18

    Item Page 21B.9.4 Erase-Verify 832 Mode Figure 21B-13 Erase/Erase-Verify Flowchart 21B.13 Programmer 840 Mode 21B.14 Flash Memory 841 and Power-Down States Table 21B-14 Flash Memory Operating States Page xviii of l Revision (See Manual for Details) Figure amended Start *1 ...

  • Page 19

    Item Page 21C.4.3 Mode 855 Transitions Figure 21C-3 Flash Memory State Transitions 21C.9.1 Program 880 Mode 21C.9.2 Program- 884 Verify Mode Figure 21C-12 Program/Program- Verify Flowchart 21C.9.3 Erase Mode 885 REJ09B0103-0800 Rev. 8.00 May 28, 2010 Revision (See Manual for ...

  • Page 20

    Item Page 21C.9.4 Erase-Verify 886 Mode Figure 21C-13 Erase/Erase-Verify Flowchart 21C.13 Programmer 894 Mode 23A.1 Overview 925 Page Revision (See Manual for Details) Figure amended Start *1 Set SWE bit in FLMCR1 ) μs Wait (t sswe ...

  • Page 21

    Item Page Section 23B Power- 947 Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F] 23B.1 Overview 950 Table 23B-2 LSI Internal States in Each Mode (H8S/2639 Group, H8S/2635 Group) ...

  • Page 22

    Item Page 24.1.3 DC 982 Characteristics Table 24-2 DC Characteristics 24.1.4 AC 985 Characteristics Figure 24-2 Output Load Circuit 24.2.3 DC 996 Characteristics Table 24-12 DC Characteristics 997 Page xxii of l Revision (See Manual for Details) Table amended Item ...

  • Page 23

    Item Page 24.2.4 AC 1002 Characteristics Figure 24-4 Output Load Circuit 24.3.3 DC 1014 Characteristics Table 24-24 DC Characteristics 1015 REJ09B0103-0800 Rev. 8.00 May 28, 2010 Revision (See Manual for Details) Figure amended LSI output pin ...

  • Page 24

    Item Page 24.3.4 AC 1020 Characteristics Figure 24-6 Output Load Circuit 24.4.3 DC 1032 Characteristics Table 24-36 DC Characteristics 1033 Page xxiv of l Revision (See Manual for Details) Figure amended LSI output pin ...

  • Page 25

    Item Page 24.4.4 AC 1038 Characteristics Figure 24-8 Output Load Circuit 24.5.4 On-Chip 1055 Supporting Module Timing Figure 24-27 HCAN 1057 Input/Output Timing REJ09B0103-0800 Rev. 8.00 May 28, 2010 Revision (See Manual for Details) Figure amended LSI output pin C ...

  • Page 26

    Item Page A.1 Instruction List 1065 Table A-1 Instruction Set (2) Arithmetic Instructions (6) Branch Instructions 1078 (7) System Control 1080 Instructions A.4 Number of States 1109 Required for Instruction Execution Table A-5 Number of Cycles in Instruction Execution Page ...

  • Page 27

    Item Page A.4 Number of States 1110 Required for Instruction Execution Table A-5 Number of Cycles in Instruction Execution 1111 Appendix B Internal 1136 to I/O Register 1421 B.2 Functions 1163 GSR0—General Status Register GSR1—General Status Register REJ09B0103-0800 Rev. 8.00 ...

  • Page 28

    Item Page B.2 Functions 1317 PFCR—Pin Function Control Register DACR01— D/A Control 1414 Register 01 Appendix C I/O Port 1422 to Block Diagrams 1451 C.1 Port 1 Block 1422 Diagrams Figure C-1 (a) Port 1 Block Diagram (Pins P10 and ...

  • Page 29

    Section 1 Overview ............................................................................................................. 1 1.1 Overview........................................................................................................................... 1 1.2 Internal Block Diagram..................................................................................................... 6 1.3 Pin Description.................................................................................................................. 9 1.3.1 Pin Arrangement .................................................................................................. 9 1.3.2 Pin Functions in Each Operating Mode ............................................................... 13 1.3.3 Pin Functions ....................................................................................................... 18 1.4 Differences between H8S/2636, ...

  • Page 30

    Exception-Handling State .................................................................................... 65 2.8.4 Program Execution State ..................................................................................... 68 2.8.5 Bus-Released State .............................................................................................. 68 2.8.6 Power-Down State ............................................................................................... 68 2.9 Basic Timing..................................................................................................................... 69 2.9.1 Overview ............................................................................................................. 69 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 69 2.9.3 On-Chip Supporting Module ...

  • Page 31

    Interrupts after Reset............................................................................................ 98 4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 99 4.3 Traces................................................................................................................................ 99 4.4 Interrupts ........................................................................................................................... 100 4.5 Trap Instruction................................................................................................................. 101 4.6 Stack Status after Exception Handling.............................................................................. 102 4.7 Notes on Use of the ...

  • Page 32

    Operation ............................................................................................................. 134 Section 6 PC Break Controller (PBC) 6.1 Overview........................................................................................................................... 137 6.1.1 Features................................................................................................................ 137 6.1.2 Block Diagram..................................................................................................... 138 6.1.3 Register Configuration......................................................................................... 139 6.2 Register Descriptions ........................................................................................................ 139 6.2.1 Break Address Register A (BARA) ..................................................................... 139 6.2.2 Break Address ...

  • Page 33

    Basic Bus Interface ........................................................................................................... 167 7.4.1 Overview.............................................................................................................. 167 7.4.2 Data Size and Data Alignment............................................................................. 167 7.4.3 Valid Strobes........................................................................................................ 169 7.4.4 Basic Timing........................................................................................................ 170 7.4.5 Wait Control ........................................................................................................ 178 7.5 Burst ROM Interface......................................................................................................... 179 7.5.1 Overview.............................................................................................................. 179 7.5.2 Basic Timing........................................................................................................ ...

  • Page 34

    Normal Mode....................................................................................................... 209 8.3.6 Repeat Mode........................................................................................................ 210 8.3.7 Block Transfer Mode ........................................................................................... 211 8.3.8 Chain Transfer ..................................................................................................... 213 8.3.9 Operation Timing................................................................................................. 214 8.3.10 Number of DTC Execution States ....................................................................... 215 8.3.11 Procedures for Using DTC .................................................................................. 217 8.3.12 Examples ...

  • Page 35

    MOS Input Pull-Up Function............................................................................... 274 9.8 Port C ................................................................................................................................ 275 9.8.1 Overview.............................................................................................................. 275 9.8.2 Register Configuration......................................................................................... 276 9.8.3 Pin Functions for Each Mode............................................................................... 279 9.8.4 MOS Input Pull-Up Function............................................................................... 281 9.9 Port D................................................................................................................................ 282 9.9.1 Overview.............................................................................................................. 282 9.9.2 Register ...

  • Page 36

    Timer Status Register (TSR)................................................................................ 338 10.2.6 Timer Counter (TCNT)........................................................................................ 342 10.2.7 Timer General Register (TGR) ............................................................................ 343 10.2.8 Timer Start Register (TSTR) ............................................................................... 344 10.2.9 Timer Synchro Register (TSYR) ......................................................................... 345 10.2.10 Module Stop Control Register A (MSTPCRA) ................................................... ...

  • Page 37

    Module Stop Control Register A (MSTPCRA) ................................................... 412 11.3 Operation .......................................................................................................................... 413 11.3.1 Overview.............................................................................................................. 413 11.3.2 Output Timing...................................................................................................... 414 11.3.3 Normal Pulse Output............................................................................................ 415 11.3.4 Non-Overlapping Pulse Output............................................................................ 417 11.3.5 Inverted Pulse Output .......................................................................................... 420 11.3.6 Pulse Output Triggered ...

  • Page 38

    Register Descriptions ........................................................................................................ 450 13.2.1 Receive Shift Register (RSR) .............................................................................. 450 13.2.2 Receive Data Register (RDR) .............................................................................. 450 13.2.3 Transmit Shift Register (TSR) ............................................................................. 451 13.2.4 Transmit Data Register (TDR)............................................................................. 451 13.2.5 Serial Mode Register (SMR) ............................................................................... 452 13.2.6 ...

  • Page 39

    Section Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) 15.1 Overview........................................................................................................................... 545 15.1.1 Features................................................................................................................ 545 15.1.2 Block Diagram..................................................................................................... 546 15.1.3 Input/Output Pins ................................................................................................. 548 15.1.4 Register Configuration......................................................................................... 549 15.2 Register Descriptions ........................................................................................................ 550 2 ...

  • Page 40

    Mailbox Configuration Register (MBCR) ........................................................... 624 16.2.5 Transmit Wait Register (TXPR) .......................................................................... 625 16.2.6 Transmit Wait Cancel Register (TXCR).............................................................. 626 16.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 627 16.2.8 Abort Acknowledge Register (ABACK) ............................................................. 628 16.2.9 Receive Complete Register (RXPR).................................................................... ...

  • Page 41

    Interface to Bus Master ..................................................................................................... 691 17.4 Operation .......................................................................................................................... 692 17.4.1 Single Mode (SCAN = 0) .................................................................................... 692 17.4.2 Scan Mode (SCAN = 1)....................................................................................... 694 17.4.3 Input Sampling and A/D Conversion Time ......................................................... 696 17.4.4 External Trigger Input Timing............................................................................. ...

  • Page 42

    Data Registers............................................................................................. 731 19.4 Operation .......................................................................................................................... 732 19.4.1 PWM Channel 1 Operation.................................................................................. 732 19.4.2 PWM Channel 2 Operation.................................................................................. 733 19.5 Usage Note........................................................................................................................ 735 Section 20 RAM .................................................................................................................. 737 20.1 Overview........................................................................................................................... 737 20.1.1 Block Diagram..................................................................................................... 737 20.1.2 Register Configuration......................................................................................... ...

  • Page 43

    Boot Mode .................................................................................................... 765 21A.8.2 User Program Mode...................................................................................... 769 21A.9 Flash Memory Programming/Erasing ........................................................................... 771 21A.9.1 Program Mode .............................................................................................. 773 21A.9.2 Program-Verify Mode .................................................................................. 774 21A.9.3 Erase Mode ................................................................................................... 778 21A.9.4 Erase-Verify Mode ....................................................................................... 779 21A.10 Protection ...................................................................................................................... 781 ...

  • Page 44

    Erase Block Register 1 (EBR1) .................................................................... 813 21B.7.4 Erase Block Register 2 (EBR2) .................................................................... 813 21B.7.5 RAM Emulation Register (RAMER) ........................................................... 814 21B.7.6 Flash Memory Power Control Register (FLPWCR)..................................... 815 21B.8 On-Board Programming Modes .................................................................................... 817 21B.8.1 Boot Mode ...

  • Page 45

    Pin Configuration .......................................................................................................... 861 21C.6 Register Configuration .................................................................................................. 862 21C.7 Register Descriptions .................................................................................................... 863 21C.7.1 Flash Memory Control Register 1 (FLMCR1) ............................................. 863 21C.7.2 Flash Memory Control Register 2 (FLMCR2) ............................................. 866 21C.7.3 Erase Block Register 1 (EBR1) .................................................................... ...

  • Page 46

    External Clock Input..................................................................................... 909 22A.4 PLL Circuit.................................................................................................................... 911 22A.5 Medium-Speed Clock Divider....................................................................................... 912 22A.6 Bus Master Clock Selection Circuit .............................................................................. 912 22A.7 Subclock Oscillator ....................................................................................................... 912 22A.8 Subclock Waveform Generation Circuit ....................................................................... 913 22A.9 Note on Crystal Resonator ............................................................................................ ...

  • Page 47

    Module Stop Mode........................................................................................................ 938 23A.5.1 Module Stop Mode ....................................................................................... 938 23A.5.2 Usage Notes .................................................................................................. 939 23A.6 Software Standby Mode ................................................................................................ 940 23A.6.1 Software Standby Mode................................................................................ 940 23A.6.2 Clearing Software Standby Mode................................................................. 940 23A.6.3 Setting Oscillation Stabilization Time after Clearing ...

  • Page 48

    Setting Oscillation Stabilization Time after Clearing Software Standby Mode............................................................................................... 967 23B.6.4 Software Standby Mode Application Example............................................. 969 23B.6.5 Usage Notes.................................................................................................. 970 23B.7 Hardware Standby Mode............................................................................................... 970 23B.7.1 Hardware Standby Mode .............................................................................. 970 23B.7.2 Hardware Standby Mode Timing ................................................................. 971 ...

  • Page 49

    Absolute Maximum Ratings .......................................................................1012 24.3.2 Power Supply Voltage and Operating Frequency Range............................1013 24.3.3 DC Characteristics ......................................................................................1014 24.3.4 AC Characteristics ......................................................................................1020 24.3.5 A/D Conversion Characteristics .................................................................1026 24.3.6 D/A Conversion Characteristics* ...............................................................1027 24.3.7 Flash Memory Characteristics ....................................................................1028 24.4 H8S/2630 Group Electrical ...

  • Page 50

    C.6 Port B Block Diagram.....................................................................................................1440 C.7 Port C Block Diagram.....................................................................................................1441 C.8 Port D Block Diagram ....................................................................................................1442 C.9 Port E Block Diagram.....................................................................................................1443 C.10 Port F Block Diagrams....................................................................................................1444 C.11 Port H Block Diagram ....................................................................................................1450 C.12 Port J Block Diagram......................................................................................................1451 Appendix D Pin ...

  • Page 51

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 1.1 Overview The H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635, and H8S/2634 are microcomputers (MCUs: microcomputer units), built around the H8S/2600 CPU, employing Renesas Electronics's proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2600 CPU ...

  • Page 52

    Section 1 Overview Table 1-1 Overview Item Specification • CPU General-register machine ⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control ⎯ Maximum clock rate: 20 MHz ...

  • Page 53

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Item Specification • 16-bit timer-pulse 6-channel 16-bit timer on-chip unit (TPU) • Pulse I/O processing capability for pins' • Automatic 2-phase encoder count capability • Programmable Maximum 8-bit pulse output possible ...

  • Page 54

    Section 1 Overview Item Specification • I/O ports 72 I/O pins, 12 input-only pins • Memory Flash memory or mask ROM • High-speed static RAM Product Name H8S/2636 H8S/2638 H8S/2639 H8S/2630 H8S/2635 H8S/2634 * Note: * The H8S/2634 is available ...

  • Page 55

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Item Specification • On-chip PLL circuit (×1, ×2, ×4) Clock pulse generator • Input clock frequency H8S/2636, H8S/2638, H8S/2630 MHz H8S/2639, H8S/2635, H8S/2634 MHz 2 • ...

  • Page 56

    Section 1 Overview 1.2 Internal Block Diagram Figure 1-1 (a) shows an internal block diagram of the H8S/2636. VCL MD2 MD1 MD0 OSC2 * 1 OSC1 * 1 EXTAL XTAL PLLCAP PLL STBY RES NMI FWE * 2 PF7/ φ ...

  • Page 57

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Figure 1-1 (b) shows an internal block diagram of the H8S/2638, H8S/2639, and H8S/2630. VCL MD2 MD1 MD0 OSC2 * 1 OSC1 * 1 EXTAL XTAL PLL PLLCAP STBY RES NMI FWE * 3 ...

  • Page 58

    Section 1 Overview Figure 1-1 (c) shows an internal block diagram of the H8S/2635 Group. VCL MD2 MD1 MD0 EXTAL XTAL PLLCAP PLLVSS STBY RES NMI FWE * 1 PF7/ φ PF6/ AS PF5/ RD PF4/ HWR ...

  • Page 59

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 1.3 Pin Description 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the H8S/2636, figure 1-3 shows the pin arrangement of the H8S/2638 and H8S/2630, figure 1-4 shows the pin arrangement of the ...

  • Page 60

    Section 1 Overview P40/AN0 103 P41/AN1 104 P42/AN2 105 P43/AN3 106 P44/AN4 107 P45/AN5 108 P46/AN6/DA0 109 P47/AN7/DA1 110 P90/AN8 111 P91/AN9 112 P92/AN10 113 P93/AN11 114 AVSS 115 MD0 116 MD1 117 MD2 118 PF0/IRQ2 119 PB7/A15/TIOCB5 120 PB6/A14/TIOCA5 ...

  • Page 61

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group P40/AN0 103 P41/AN1 104 P42/AN2 105 P43/AN3 106 P44/AN4 107 P45/AN5 108 P46/AN6/DA0 109 P47/AN7/DA1 110 P90/AN8 111 P91/AN9 112 P92/AN10 113 P93/AN11 114 AVSS 115 MD0 116 MD1 117 MD2 118 PF0/IRQ2 119 ...

  • Page 62

    Section 1 Overview P40/AN0 103 P41/AN1 104 P42/AN2 105 P43/AN3 106 P44/AN4 107 P45/AN5 108 P46/AN6 109 P47/AN7 110 P90/AN8 111 P91/AN9 112 P92/AN10 113 P93/AN11 114 AVSS 115 MD0 116 MD1 117 MD2 118 PF0/IRQ2 119 PB7/A15/TIOCB5 120 PB6/A14/TIOCA5 ...

  • Page 63

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 1.3.2 Pin Functions in Each Operating Mode Table 1-2 shows the pin functions for each operating mode. Table 1-2 Pin Functions in Each Operating Mode Pin No. FP-128B Mode 4 1 VCC 2 VCC ...

  • Page 64

    Section 1 Overview Pin No. FP-128B Mode 4 27 PE7/D7 28 PE6/D6 29 PE5/D5 30 PE4/D4 31 PE3/D3 32 PE2/D2 33 PE1/D1 34 PE0/D0 35 VSS 36 VSS 37 HRxD1 38 HTxD1 HWR 41 LWR/ADTRG/ 42 ...

  • Page 65

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Pin No. FP-128B Mode 4 57 PJ2/PWM2C 58 PJ3/PWM2D 59 PWMVCC 60 PJ4/PWM2E 61 PJ5/PWM2F 62 PJ6/PWM2G 63 PJ7/PWM2H 64 PWMVSS 65 P30/TxD0 66 P31/RxD0 67 VSS 68 VSS P32/SCK0/SDA1 * ...

  • Page 66

    Section 1 Overview Pin No. FP-128B Mode 4 STBY 87 88 PF7/φ P10/PO8 * 4 /TIOCA0/A20 P10/PO8 * 89 P11/PO9 * 4 /TIOCB0/A21 P11/PO9 * 90 4 P12/PO10 * 91 /TIOCC0/ TCLKA/A22 P13/PO11 * 4 92 /TIOCD0/ TCLKB/A23 P14/PO12 * ...

  • Page 67

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Pin No. FP-128B Mode 4 113 P92/AN10 114 P93/AN11 115 AVSS 116 MD0 117 MD1 118 MD2 119 PF0/IRQ2 120 PB7/A15/TIOCB5 121 PB6/A14/TIOCA5 122 PB5/A13/TIOCB4 123 PB4/A12/TIOCA4 124 PB3/A11/TIOCD3 125 PB2/A10/TIOCC3 126 PB1/A9/TIOCB3 127 ...

  • Page 68

    Section 1 Overview 1.3.3 Pin Functions Table 1-3 outlines the pin functions of the H8S/2636. Table 1-3 Pin Functions Type Symbol Power VCC VSS VCL Clock PLLVSS PLLCAP XTAL EXTAL 1 OSC1 * 1 OSC2 * φ HCAN HTxD0, 3 ...

  • Page 69

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Type Symbol Operating mode MD2 to MD0 control RES System control STBY 2 FWE * Interrupts NMI IRQ5 to IRQ0 Input Address bus A23 to A0 Data bus D15 Bus control ...

  • Page 70

    Section 1 Overview Type Symbol LWR Bus control 16-bit timer- TCLKD to pulse unit (TPU) TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4 TIOCA5, TIOCB5 Programmable PO15 to 4 PO8 * pulse generator ...

  • Page 71

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Type Symbol DA1, DA0 * D/A converter A/D converter, AVCC D/A converter AVSS Vref I/O ports P17 to P10 P35 to P30 P47 to P40 P93 to P90 PA3 to PA0 PB7 to PB0 ...

  • Page 72

    Section 1 Overview Type Symbol I/O ports PF7 to PF3, PF0 PH7 to PH0 PJ7 to PJ0 Motor control PWM1A to PWM PWM1H PWM2A to PWM2H PWMVCC PWMVSS bus interface SCL0, SCL1 (IIC) (Optionk) (Only for the ...

  • Page 73

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 1.4 Differences between H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635, and H8S/2634 There are four versions of the H8S/2636, including ROM and U-mask options; there are six versions of the H8S/2638, including ROM, U-mask, and W-mask ...

  • Page 74

    Section 1 Overview Part No. Model H8S/2639 * HD64F2639UF 256-kbyte on-chip HD64F2639WF flash memory HD6432639UF 256-kbyte mask ROM HD6432639WF H8S/2630 HD64F2630F 384-kbyte on-chip flash memory HD64F2630UF HD64F2630WF HD6432630F 384-kbyte mask ROM HD6432630UF HD6432630WF H8S/2635 * HD64F2635F 192-kbyte on-chip flash memory ...

  • Page 75

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 2.1 Overview The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can ...

  • Page 76

    Section 2 CPU • High-speed operation ⎯ All frequently-used instructions execute in one or two states ⎯ Maximum clock rate ⎯ 8/16/32-bit register-register add/subtract : 50 ns ⎯ 8 × 8-bit register-register multiply ⎯ 16 ÷ 8-bit register-register divide ⎯ ...

  • Page 77

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU ...

  • Page 78

    Section 2 CPU 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements. • Additional control register ⎯ One 8-bit and two 32-bit control registers have been added • Enhanced instructions ⎯ ...

  • Page 79

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group (1) Normal Mode (Not Available in the Chip) The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be ...

  • Page 80

    Section 2 CPU bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. Stack Structure: When the program counter (PC) is pushed ...

  • Page 81

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the ...

  • Page 82

    Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception ...

  • Page 83

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 2.3 Address Space Figure 2-6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) ...

  • Page 84

    Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2-7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ...

  • Page 85

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used ...

  • Page 86

    Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-9 shows the stack. SP (ER7) 2.4.3 Control Registers The ...

  • Page 87

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR ...

  • Page 88

    Section 2 CPU The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to ...

  • Page 89

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit …, ...

  • Page 90

    Section 2 CPU Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General ...

  • Page 91

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 2.5.2 Memory Data Formats Figure 2-11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. ...

  • Page 92

    Section 2 CPU 2.6 Instruction Set 2.6.1 Overview The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2-1. Table 2-1 Instruction Classification Function Instructions Data transfer MOV 1 POP * , PUSH * ...

  • Page 93

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 2.6.2 Instructions and Addressing Modes Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2-2 Combinations of Instructions and Addressing Modes ⎯ @@aa:8 @(d:16,PC) @(d:8,PC) @aa:32 ...

  • Page 94

    Section 2 CPU ⎯ @@aa:8 @(d:16,PC) @(d:8,PC) @aa:32 @aa:24 @aa:16 @aa:8 @−ERn/@ERn+ @(d:32,ERn) @(d:16,ERn) @ERn Rn #xx Page 44 of 1458 H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group REJ09B0103-0800 Rev. 8.00 May 28, 2010 ...

  • Page 95

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 2.6.3 Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation General register (destination General register ...

  • Page 96

    Section 2 CPU Table 2-3 Instructions Classified by Function Type Instruction Data transfer MOV MOVFPE MOVTPE POP PUSH 2 LDM * 2 STM * Page 46 of 1458 1 Size * Function (EAs) → Rd, Rs → (EAd) B/W/L Moves ...

  • Page 97

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Type Instruction Arithmetic ADD operations SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS DIVXU REJ09B0103-0800 Rev. 8.00 May 28, 2010 1 Size * Function Rd ± Rs → Rd, Rd ± ...

  • Page 98

    Section 2 CPU Type Instruction Arithmetic DIVXS operations CMP NEG EXTU EXTS TAS MAC CLRMAC LDMAC STMAC Page 48 of 1458 1 Size * Function Rd ÷ Rs → Rd B/W Performs signed division on data in two general registers: ...

  • Page 99

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Type Instruction Logic AND operations OR XOR NOT Shift SHAL operations SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR REJ09B0103-0800 Rev. 8.00 May 28, 2010 1 Size * Function Rd ∧ Rs → Rd, Rd ...

  • Page 100

    Section 2 CPU Type Instruction Bit- BSET manipulation instructions BCLR BNOT BTST BAND BIAND BOR BIOR Page 50 of 1458 1 Size * Function 1 → (<bit-No.> of <EAd>) B Sets a specified bit in a general register or memory ...

  • Page 101

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Type Instruction Bit- BXOR manipulation instructions BIXOR BLD BILD BST BIST REJ09B0103-0800 Rev. 8.00 May 28, 2010 1 Size * Function C ⊕ (<bit-No.> of <EAd>) → Exclusive-ORs the carry flag with ...

  • Page 102

    Section 2 CPU Type Instruction Branch Bcc instructions JMP BSR JSR RTS Page 52 of 1458 1 Size * Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) ...

  • Page 103

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Type Instruction System control TRAPA instructions RTE SLEEP LDC STC ANDC ORC XORC NOP REJ09B0103-0800 Rev. 8.00 May 28, 2010 1 Size * Function — Starts trap-instruction exception handling. — Returns from an exception-handling ...

  • Page 104

    Section 2 CPU Type Instruction Block data EEPMOV.B transfer instruction EEPMOV.W Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only registers ER0 to ER6 should be used when using the STM/LDM instruction. 3. ...

  • Page 105

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group (4) Condition Field: Specifies the branching condition of Bcc instructions. Figure 2-12 shows examples of instruction formats. (1) Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and ...

  • Page 106

    Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the ...

  • Page 107

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group (4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. ...

  • Page 108

    Section 2 CPU (6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit ...

  • Page 109

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Specified Branch address by @aa:8 (a) Normal Mode * Note: * Not available in the chip. Figure 2-13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or ...

  • Page 110

    Section 2 CPU Table 2.6 Effective Address Calculation Page 60 of 1458 H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group REJ09B0103-0800 Rev. 8.00 May 28, 2010 ...

  • Page 111

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group REJ09B0103-0800 Rev. 8.00 May 28, 2010 Section 2 CPU Page 61 of 1458 ...

  • Page 112

    Section 2 CPU Page 62 of 1458 H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group REJ09B0103-0800 Rev. 8.00 May 28, 2010 ...

  • Page 113

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 2.8 Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the processing ...

  • Page 114

    Section 2 CPU Bus-released state Exception handling state RES = High Reset state * Reset state From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. goes low. A transition can also ...

  • Page 115

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, trace, interrupt, or trap instruction. The CPU fetches a start ...

  • Page 116

    Section 2 CPU (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. The CPU enters the reset state when the RES is ...

  • Page 117

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group *2 Normal mode SP CCR *1 CCR PC (16 bits) (a) Interrupt control mode 0 Advanced mode SP CCR PC (24 bits) (c) Interrupt control mode 0 Notes: 1. Ignored when returning. 2. Not ...

  • Page 118

    Section 2 CPU 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus ...

  • Page 119

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 2.9 Basic Timing 2.9.1 Overview The H8S/2600 CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge of φ to the next is referred to as ...

  • Page 120

    Section 2 CPU φ Address bus AS RD HWR, LWR Data bus Figure 2-18 Pin States during On-Chip Memory Access Page 70 of 1458 Bus cycle T 1 Unchanged High High High High-impedance state H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group ...

  • Page 121

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being ...

  • Page 122

    Section 2 CPU φ Address bus AS RD HWR, LWR Data bus Figure 2-20 Pin States during On-Chip Supporting Module Access Page 72 of 1458 H8S/2639, H8S/2638, H8S/2636, Bus cycle Unchanged High High High High-impedance state ...

  • Page 123

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 2.9.4 On-Chip HCAN Module Access Timing On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait states can be inserted by means of a wait request from ...

  • Page 124

    Section 2 CPU φ Internal address bus HCAN read signal Read Internal data bus HCAN write signal Write Internal data bus Figure 2-22 On-Chip HCAN Module Access Cycle (Wait States Inserted) φ Address bus AS RD HWR, LWR Data bus ...

  • Page 125

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 2.9.5 Port H and J Register Access Timing Accesses to port H and J registers and the on-chip motor control PWM timer module are performed in four states. The data bus width is 8 ...

  • Page 126

    Section 2 CPU φ Address bus AS RD HWR, LWR Data bus Figure 2-25 Pin States in Access to Ports H and J Registers and On-Chip Motor Control 2.9.6 External Address Space Access Timing The external address space is accessed ...

  • Page 127

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 2.10 Usage Note 2.10.1 TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas Electronics H8S Family and ...

  • Page 128

    Section 2 CPU Page 78 of 1458 H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group REJ09B0103-0800 Rev. 8.00 May 28, 2010 ...

  • Page 129

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The chip has four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, ...

  • Page 130

    Section 3 MCU Operating Modes Note that the functions of each pin depend on the operating mode. The chip can be used only in modes This means that the mode pins must be set to select one ...

  • Page 131

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Bit 7—Reserved: Only 1 should be written to these bits. Bits 6 to 3—Reserved: These bits are always read as 0 and cannot be modified. Bits 2 to 0—Mode Select (MDS2 ...

  • Page 132

    Section 3 MCU Operating Modes Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and ...

  • Page 133

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 3.2.3 Pin Function Control Register (PFCR) Bit : 7 ⎯ Initial value : 0 R/W : R/W PFCR is an 8-bit readable-writeable register that performs address output control in on-chip ROM- enabled expansion mode. ...

  • Page 134

    Section 3 MCU Operating Modes Bit 3 Bit 2 Bit 1 Bit 0 AE3 AE2 AE1 AE0 ...

  • Page 135

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 3.3 Operating Mode Descriptions 3.3.1 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports and C function as an address bus, ...

  • Page 136

    Section 3 MCU Operating Modes 3.3.4 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. ...

  • Page 137

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 3.5 Address Map in Each Operating Mode An address map of the H8S/2636 is shown in figure 3-1. An address map of the H8S/2638 and H8S/2639 is shown in figure 3-2. An address map ...

  • Page 138

    Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFAFFF H'FFB000 Reserved area H'FFDFFF H'FFE000 On-chip RAM* H'FFEFBF H'FFEFC0 External address space H'FFF7FF H'FFF800 Internal I/O registers H'FFFF3F H'FFFF40 ...

  • Page 139

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFAFFF H'FFB000 On-chip RAM* H'FFEFBF H'FFEFC0 External address space H'FFF7FF H'FFF800 Internal I/O registers H'FFFF3F H'FFFF40 External address space ...

  • Page 140

    Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFAFFF H'FFB000 On-chip RAM* H'FFEFBF H'FFEFC0 External address space H'FFF7FF H'FFF800 Internal I/O registers H'FFFF3F H'FFFF40 External address space H'FFFF5F ...

  • Page 141

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFAFFF H'FFB000 Reserved area H'FFD7FF H'FFD800 On-chip RAM* H'FFEFBF H'FFEFC0 External address space H'FFF7FF H'FFF800 Internal I/O registers H'FFFF3F ...

  • Page 142

    Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFAFFF H'FFB000 Reserved area H'FFD7FF H'FFD800 On-chip RAM* H'FFEFBF H'FFEFC0 External address space H'FFF7FF H'FFF800 Internal I/O registers H'FFFF3F H'FFFF40 ...

  • Page 143

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trace, direct transition * , trap instruction, or interrupt. Exception ...

  • Page 144

    Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. ...

  • Page 145

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Table 4-2 Exception Vector Table Exception Source Reset Reserved for system use Trace 3 Direct Transition * External interrupt NMI Trap instruction (4 sources) Reserved for system use External interrupt IRQ0 IRQ1 IRQ2 IRQ3 ...

  • Page 146

    Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all current operations are stopped, and this LSI enters reset state. A reset initializes the internal state of the ...

  • Page 147

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group φ RES Internal address bus Internal read signal Internal write signal Internal data bus (1) (3) Reset exception handling vector address (when power-on reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address ...

  • Page 148

    Section 4 Exception Handling φ RES Address bus RD HWR, LWR D15 to D0 (1) (3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) ...

  • Page 149

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 4.2.4 State of On-Chip Supporting Modules after Reset Release After reset release, MSTPCRA to MSTPCRD are initialized to H'3F, H'FF, H'FF, and *1 B'11****** , respectively, and all modules except the DTC, enter module ...

  • Page 150

    Section 4 Exception Handling 4.4 Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ5 to IRQ0) and 49 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and the number of interrupts ...

  • Page 151

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a ...

  • Page 152

    Section 4 Exception Handling 4.6 Stack Status after Exception Handling Figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP CCR CCR* PC (16 bits) (a) Interrupt control mode 0 Note: * Ignored ...

  • Page 153

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 4.7 Notes on Use of the Stack When accessing word data or longword data, the chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction ...

  • Page 154

    Section 4 Exception Handling Page 104 of 1458 H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group REJ09B0103-0800 Rev. 8.00 May 28, 2010 ...

  • Page 155

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The chip controls interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two interrupt control modes ⎯ Any of two ...

  • Page 156

    Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5-1. INTM1, INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISCR Internal interrupt request SWDTEND to RM0 ...

  • Page 157

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 5.1.3 Pin Configuration Table 5-1 summarizes the pins of the interrupt controller. Table 5-1 Interrupt Controller Pins Name Symbol Nonmaskable interrupt NMI IRQ5 to IRQ0 Input External interrupt requests 5.1.4 Register ...

  • Page 158

    Section 5 Interrupt Controller 5.2 Register Descriptions Note: The H8S/2635 Group is not equipped with a DTC brake controller HCAN1. 5.2.1 System Control Register (SYSCR) 7 Bit : MACS 0 Initial value : R/W R/W : ...

  • Page 159

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 5.2.2 Interrupt Priority Registers (IPRA to IPRH, IPRJ to IPRM) Bit : 7 ⎯ Initial value : 0 ⎯ R/W : The IPR registers are twelve 8-bit readable/writable ...

  • Page 160

    Section 5 Interrupt Controller As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits and sets ...

  • Page 161

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH Bit : 15 ⎯ Initial value : 0 R/W : R/W ISCRL 7 Bit : IRQ3SCB IRQ3SCA 0 Initial value : R/W R/W ...

  • Page 162

    Section 5 Interrupt Controller 5.2.5 IRQ Status Register (ISR) Bit : 7 ⎯ Initial value : 0 R/W : R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates ...

  • Page 163

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Bit n IRQnF Description 0 [Clearing conditions] • Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag • When interrupt exception handling is executed when low-level detection is ...

  • Page 164

    Section 5 Interrupt Controller 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ5 to IRQ0) and internal interrupts (49 sources). Note: The H8S/2635 Group is not equipped with a DTC brake controller HCAN1. The ...

  • Page 165

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 5-2. IRQnSCA, IRQnSCB Edge/level detection circuit IRQn input Note Figure 5-2 Block Diagram of Interrupts IRQ5 to ...

  • Page 166

    Section 5 Interrupt Controller 5.3.2 Internal Interrupts There are 49 sources for internal interrupts from on-chip supporting modules. • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or ...

  • Page 167

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved for system use SWDTEND (software activation interrupt end) WOVI0 (interval timer) Reserved for system use ...

  • Page 168

    Section 5 Interrupt Controller Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) TGI3A (TGR3A ...

  • Page 169

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Interrupt Source TGI5A (TGR5A input capture/compare match) TGI5B (TGR5B input capture/compare match) TCI5V (overflow 5) TCI5U (underflow 5) Reserved for system use ERI0 (receive error 0) RXI0 (reception completed 0) TXI0 (transmit data empty ...

  • Page 170

    Section 5 Interrupt Controller Interrupt Source PWM1 PWM2 ERS0, OVR0, RM1, SLE0, RM0 ERS0, OVR0, RM1, SLE0, RM0 Reserved for system use Notes: 1. Lower 16 bits of the start address available as an option ...

  • Page 171

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Table 5-5 Interrupt Control Modes SYSCR Interrupt Control Mode INTM1 INTM0 — — 1 Figure 5-4 shows a block diagram of the priority decision circuit. Interrupt source ...

  • Page 172

    Section 5 Interrupt Controller (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5-6 shows the interrupts selected in each interrupt control mode. Table 5-6 Interrupts Selected in Each ...

  • Page 173

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group (3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts ...

  • Page 174

    Section 5 Interrupt Controller 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit ...

  • Page 175

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group IRQ0 Yes Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in REJ09B0103-0800 Rev. 8.00 May 28, 2010 Program execution status Interrupt generated? Yes Yes NMI Yes No IRQ1 Yes ...

  • Page 176

    Section 5 Interrupt Controller 5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits EXR in the CPU with IPR. ...

  • Page 177

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in REJ09B0103-0800 Rev. 8.00 May 28, 2010 Program execution status No Interrupt generated? Yes Yes ...

  • Page 178

    Section 5 Interrupt Controller 5.4.4 Interrupt Exception Handling Sequence Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack ...

  • Page 179

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 5.4.5 Interrupt Response Times The chip is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed ...

  • Page 180

    Section 5 Interrupt Controller Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses Symbol Instruction fetch Branch address read Stack manipulation Legend: m: Number of wait states in an external device access. 5.5 Usage Notes 5.5.1 Contention between ...

  • Page 181

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group φ Internal address bus Internal write signal TCIEV TCFV TCFV interrupt signal Figure 5-8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag ...

  • Page 182

    Section 5 Interrupt Controller 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the ...

  • Page 183

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 5.6 DTC Activation by Interrupt Note: The DTC is not implemented in the H8S/2635 Group. 5.6.1 Overview The DTC can be activated by an interrupt. In this case, the following options are available: • ...

  • Page 184

    Section 5 Interrupt Controller 5.6.3 Operation The interrupt controller has three main functions in DTC control. (1) Selection of Interrupt Source: Interrupt factors are selected as DTC activation request or CPU interrupt request by the DTCE bit of DTCERA to ...

  • Page 185

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Table 5-11 Interrupt Source Selection and Clearing Control Settings DTC DTCE DISEL Legend: Δ : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear ...

  • Page 186

    Section 5 Interrupt Controller Page 136 of 1458 H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group REJ09B0103-0800 Rev. 8.00 May 28, 2010 ...

  • Page 187

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Section 6 PC Break Controller (PBC) Note: The H8S/2635 Group is not equipped with a PBC. 6.1 Overview The PC break controller (PBC) provides functions that simplify program debugging. Using these functions ...

  • Page 188

    Section 6 PC Break Controller (PBC) 6.1.2 Block Diagram Figure 6-1 shows a block diagram of the PC break controller. BARA Comparator Internal address Access status Comparator BARB Figure 6-1 Block Diagram of PC Break Controller Page 138 of 1458 ...

  • Page 189

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 6.1.3 Register Configuration Table 6-1 shows the PC break controller registers. Table 6-1 PC Break Controller Registers Name Break address register A Break address register B Break control register A Break control register B ...

  • Page 190

    Section 6 PC Break Controller (PBC) 6.2.2 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Break Control Register A (BCRA) 7 Bit CMFA Initial value ...

  • Page 191

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Bit 6—CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break condition bus master. Bit 6 CDA Description 0 PC break is performed when CPU is bus master 1 PC break is performed ...

  • Page 192

    Section 6 PC Break Controller (PBC) Bits 2 and 1—Break Condition Select A (CSELA1, CSELA0): These bits selection an instruction fetch, data read, data write, or data read/write cycle as the channel A break condition. Bit 2 Bit 1 CSELA1 ...

  • Page 193

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Bit 4 MSTPC4 Description 0 PC break controller module stop mode is cleared 1 PC break controller module stop mode is set 6.3 Operation The operation flow from break condition setting to PC break ...

  • Page 194

    Section 6 PC Break Controller (PBC) 6.3.2 PC Break Interrupt Due to Data Access (1) Initial settings ⎯ Set the break address in BARA. For a PC break caused by a data access, set the target ROM, RAM, I/O, or ...

  • Page 195

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 6.3.4 Operation in Transitions to Power-Down Modes The operation when a PC break interrupt is set for an instruction fetch at the address after a SLEEP instruction is shown below. (1) When the SLEEP ...

  • Page 196

    Section 6 PC Break Controller (PBC) SLEEP instruction SLEEP instruction execution PC break exception System clock → subclock* handling Execution of instruction Direct transition* after sleep instruction exception handling (A) PC break exception Execution of instruction after sleep instruction Note: ...

  • Page 197

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group 6.3.6 When Instruction Execution Is Delayed by One State Caution is required in the following cases, as instruction execution is one state later than usual. (1) When the PBC is enabled (i.e. when the ...

  • Page 198

    Section 6 PC Break Controller (PBC) 6.3.7 Additional Notes (1) When a PC break is set for an instruction fetch at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction: Even if the instruction at the address ...

  • Page 199

    H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Section 7 Bus Controller 7.1 Overview The chip has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of ...

  • Page 200

    Section 7 Bus Controller 7.1.2 Block Diagram Figure 7-1 shows a block diagram of the bus controller. External bus control signals Legend: ABWCR: Bus width control register ASTCR: Access state control register BCRH: Bus control register H BCRL: Bus control ...