HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 973
HD64F2638F20J
Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2638F20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
22B.4 PLL Circuit
The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a
factor of 1, 2, or 4. The multiplication factor is set with the STC bits in SCKCR. The phase of the
rising edge of the internal clock is controlled so as to match that at the EXTAL pin.
When the multiplication factor of the PLL circuit is changed, the operation varies according to the
setting of the STCS bit in SCKCR.
When STCS = 0 (initial value), the setting becomes valid after a transition to software standby
mode, watch mode, or subactive mode. The transition time count is performed in accordance with
the setting of bits STS2 to STS0 in SBYCR.
[1] The initial PLL circuit multiplication factor is 1.
[2] A value is set in bits STS2 to STS0 to give the specified transition time.
[3] The target value is set in STC1 and STC0, and a transition is made to software standby mode,
[4] The clock pulse generator stops and the value set in STC1 and STC0 becomes valid.
[5] Software standby mode, watch mode, or subactive mode is cleared, and a transition time is
[6] After the set transition time has elapsed, the LSI resumes operation using the target
If a PC break is set for the SLEEP instruction that causes a transition to software standby mode in
[1], software standby mode is entered and break exception handling is executed after the
oscillation stabilization time. In this case, the instruction following the SLEEP instruction is
executed after execution of the RTE instruction.
When STCS = 1, the LSI operates on the changed multiplication factor immediately after bits
STC1 and STC0 are rewritten.
22B.5 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32.
22B.6 Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed
clocks (φ/2, φ/4, or φ/8, φ/16, and φ/32) to be supplied to the bus master, according to the settings
of the SCK2 to SCK0 bits in SCKCR.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
watch mode, or subactive mode.
secured in accordance with the setting in STS2 to STS0.
multiplication factor.
Section 22B Clock Pulse Generator
(H8S/2639 Group, H8S/2635 Group)
Page 923 of 1458
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