HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 620

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
Section 15 I
(Only for the H8S/2638, H8S/2639, and H8S/2630)
Bit 3—Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The
I
nearly the same time, if the I
to 1 to indicate that the bus has been taken by another master.
AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is
reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 3
AL
0
1
Bit 2—Slave Address Recognition Flag (AAS): In I
set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the
general call address (H'00) is detected.
AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Page 570 of 1458
2
C bus interface monitors the bus. When two or more master devices attempt to seize the bus at
2
C Bus Interface [Option]
Bus arbitration won
[Clearing conditions]
Arbitration lost
[Setting conditions]
Description
When ICDR data is written (transmit mode) or read (receive mode)
When 0 is written in AL after reading AL = 1
If the internal SDA and SDA pin disagree at the rise of SCL in master transmit
mode
If the internal SCL line is high at the fall of SCL in master transmit mode
2
C bus interface detects data differing from the data it sent, it sets AL
2
C bus format slave receive mode, this flag is
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
(Initial value)
May 28, 2010

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