HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 590

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 14 Smart Card Interface
Software
standby
Normal operation
Normal operation
[1] [2] [3]
[4] [5]
[6] [7]
Figure 14-9 Clock Halt and Restart Procedure
Powering On: To secure the clock duty from power-on, the following switching procedure should
be followed.
[1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor
to fix the potential.
[2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR.
[3] Set SMR and SCMR, and switch to smart card mode operation.
[4] Set the CKE0 bit in SCR to 1 to start clock output.
14.3.8
Operation in Block Transfer Mode
Operation in block transfer mode is the same as in SCI asynchronous mode, except for the
following points. For details, see section 13.3.2, Operation in Asynchronous Mode.
Data Format: The data format is 8 bits with parity. There is no stop bit, but there is a 2-bit (1-bit
or more in reception) error guard time.
Also, except during transmission (with start bit, data bits, and parity bit), the transmission pins go
to the high-impedance state, so the signal lines must be fixed high with a pull-up resistor.
Transmit/Receive Clock: Only an internal clock generated by the on-chip baud rate generator can
be used as the transmit/receive clock. The number of basic clock periods in a 1-bit transfer interval
can be set to 32, 64, 372, or 256 with bits BCP1 and BCP0. For details, see section 14.3.5, Clock.
ERS (FER) Flag: As with the normal Smart Card interface, the ERS flag indicates the error signal
status, but since error signal transmission and reception is not performed, this flag is always
cleared to 0.
Page 540 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010