HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 634
HD64F2638F20J
Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2638F20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Manufacturer
Quantity
Price
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Part Number:
HD64F2638F20J
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PENESAS
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Section 15 I
(Only for the H8S/2638, H8S/2639, and H8S/2630)
The procedure for receiving data sequentially, using the wait states (WAIT bit) for
synchronization with ICDR (ICDRR) read operations, is described below.
The procedure below describes the operation for receiving multiple bytes. Note that some of the
steps are omitted when receiving only 1 byte. Refer to figure 15-11 for details.
Page 584 of 1458
Figure 15-11 Flowchart for Master Receive Mode (Receiving 1 Byte) (WAIT = 1)
2
C Bus Interface [Option]
No
No
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Set ACKB = 0 (ICSR)
Set ACKB = 1 (ICSR)
Set WAIT = 1 (ICMR)
Set WAIT = 0 (ICMR)
Master receive mode
and SCP = 0 (ICCR)
Set TRS = 0 (ICCR)
Set TRS = 1 (ICCR)
Write BBSY = 0
Read ICDR
Read ICDR
IRIC = 1?
IRIC = 1?
End
Yes
Yes
(Example)
[1]
[2]
[3]
[7]
[9]
[11] Clear IRIC flag (cancel wait state)
[12] Wait for end of reception of 1 byte
[15] Cancel wait mode
[16] Read final receive data
[17] Generate stop condition
Set to receive mode
Receive start, dummy read
Receive wait state (IRIC set at falling edge
of 8th clock cycle) or
Wait for end of reception of 1 byte
(IRIC set at rising edge of 9th clock cycle)
Set acknowledge data for final receive
Set TRS to generate stop condition
(IRIC set at rising edge of 9th clock cycle)
Clear IRIC flag (IRIC flag should be
cleared when WAIT = 0)
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
May 28, 2010
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