HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 614

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 15 I
(Only for the H8S/2638, H8S/2639, and H8S/2630)
Bit 1
IRIC
0
1
Page 564 of 1458
2
C Bus Interface [Option]
Waiting for transfer, or transfer in progress
[Clearing conditions]
•
•
Interrupt requested
[Setting conditions]
I
•
•
•
•
•
I
•
•
•
•
•
Synchronous serial format
•
•
When any other condition arises in which the TDRE or RDRF flag is set to 1
Description
2
2
C bus format master mode
C bus format slave mode
When 0 is written in IRIC after reading IRIC = 1
When ICDR is written or read by the DTC
(When the TDRE or RDRF flag is cleared to 0)
(This is not always a clearing condition; see the description of DTC operation for
details)
When a start condition is detected in the bus line state after a start condition is
issued (when the TDRE flag is set to 1 because of first frame transmission)
When a wait is inserted between the data and acknowledge bit when WAIT = 1
At the end of data transfer
(at the rise of the 9th transmit/receive clock pulse, or at the fall of the 8th
transmit/receive clock pulse when using wait insertion)
When a slave address is received after bus arbitration is lost (when the AL flag is
set to 1)
When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the
ACKB bit is set to 1)
When the slave address (SVA, SVAX) matches (when the AAS and AASX flags
are set to 1)
and at the end of data transfer up to the subsequent retransmission start condition
or stop condition detection (when the TDRE or RDRF flag is set to 1)
When the general call address is detected (when FS = 0 and the ADZ flag is set to
1) and at the end of data transfer up to the subsequent retransmission start
condition or stop condition detection (when the TDRE or RDRF flag is set to 1)
When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the
ACKB bit is set to 1)
When a stop condition is detected (when the STOP or ESTP flag is set to 1)
At the end of data transfer (when the TDRE or RDRF flag is set to 1)
When a start condition is detected with serial format selected
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
(Initial value)
May 28, 2010