HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 605

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit 0—Format Select X (FSX): Used together with the FS bit in SAR to select the
communication format.
• I
• Synchronous serial format: non-addressing format without acknowledge bit, for master mode
The FSX bit also specifies whether or not SARX slave address recognition is performed in slave
mode. For details, see the description of the FS bit in SAR.
15.2.4
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs master mode wait control, and selects the master mode transfer clock frequency and
the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written and
read only when the ICE bit is set to 1 in ICCR.
ICMR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or
LSB-first.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
Do not set this bit to 1 when the I
Bit 7
MLS
0
1
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Bit
Initial value :
R/W
only
2
C bus format: addressing format with acknowledge bit
I
2
C Bus Mode Register (ICMR)
Description
MSB-first
LSB-first
:
:
MLS
R/W
7
0
WAIT
R/W
6
0
2
C bus format is used.
CKS2
R/W
5
0
CKS1
R/W
4
0
CKS0
(Only for the H8S/2638, H8S/2639, and H8S/2630)
R/W
3
0
Section 15 I
BC2
R/W
2
0
2
BC1
R/W
C Bus Interface [Option]
1
0
(Initial value)
Page 555 of 1458
BC0
R/W
0
0