HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 612
HD64F2638F20J
Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2638F20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
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Section 15 I
(Only for the H8S/2638, H8S/2639, and H8S/2630)
Bit 3—Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the
acknowledge bit returned from the receiving device when using the I
and continuous transfer is performed, or transfer is to be aborted and error handling, etc.,
performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received
acknowledge bit is not indicated by the ACKB bit, which is always 0.
In this LSI, the DTC can be used to perform continuous transfer. The DTC is activated when the
IRTR interrupt flag is set to 1 (IRTR is one of two interrupt flags, the other being IRIC). When the
ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on completion of data transmission,
regardless of the value of the acknowledge bit. When the ACKE bit is 1, the TDRE, IRIC, and
IRTR flags are set on completion of data transmission when the acknowledge bit is 0, and the
IRIC flag alone is set on completion of data transmission when the acknowledge bit is 1.
When the DTC is activated, the TDRE, IRIC, and IRTR flags are cleared to 0 after the specified
number of data transfers have been executed. Consequently, interrupts are not generated during
continuous data transfer, but if data transmission is completed with a 1 acknowledge bit when the
ACKE bit is set to 1, the DTC is not activated and an interrupt is generated, if enabled.
Depending on the receiving device, the acknowledge bit may be significant, in indicating
completion of processing of the received data, for instance, or may be fixed at 1 and have no
significance.
Bit 3
ACKE
0
1
Page 562 of 1458
2
C Bus Interface [Option]
Description
The value of the acknowledge bit is ignored, and continuous transfer is performed
If the acknowledge bit is 1, continuous transfer is interrupted
2
C bus format is to be ignored
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
(Initial value)
May 28, 2010
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