HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 557

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Restrictions on Use of DTC *
Note: * The DTC is not implemented in the H8S/2635 Group.
• When an external clock source is used as the serial clock, the transmit clock should not be
• When RDR is read by the DTC, be sure to set the activation source to the relevant SCI
Operation in Case of Mode Transition
• Transmission
Note: * The DTC is not implemented in the H8S/2635 Group.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
input until at least 5 φ clock cycles after TDR is updated by the DTC. Misoperation may occur
if the transmit clock is input within 4 φ clocks after TDR is updated (figure 13-22).
reception end interrupt (RXI).
Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module
stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition.
TSR, TDR, and SSR are reset. The output pin states in module stop mode, software standby
mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and
becomes high-level output after the relevant mode is cleared. If a transition is made during
transmission, the data being transmitted will be undefined. When transmitting without
changing the transmit mode after the relevant mode is cleared, transmission can be started by
setting TE to 1 again, and performing the following sequence: SSR read -> TDR write ->
TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode,
the procedure must be started again from initialization. Figure 13-23 shows a sample flowchart
for mode transition during transmission. Port pin states are shown in figures 13-24 and 13-25.
Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a
transition from transmission by DTC * transfer to module stop mode, software standby mode,
watch mode, subactive mode, or subsleep mode transition. To perform transmission with the
DTC * after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start
DTC * transmission.
SCK
TDRE
Serial data
Note: When operating on an external clock, set t > 4 clocks.
Figure 13-22 Example of Clocked Synchronous Transmission by DTC
t
LSB
D0
D1
D2
D3
D4
Section 13 Serial Communication Interface (SCI)
D5
D6
D7
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