IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part NumberHD64F2638F20J
DescriptionIC H8S MCU FLASH 256K 128-QFP
ManufacturerRenesas Electronics America
SeriesH8® H8S/2600
HD64F2638F20J datasheets
 


Specifications of HD64F2638F20J

Core ProcessorH8S/2600Core Size16-Bit
Speed20MHzConnectivityCAN, SCI, SmartCard
PeripheralsMotor Control PWM, POR, PWM, WDTNumber Of I /o72
Program Memory Size256KB (256K x 8)Program Memory TypeFLASH
Ram Size16K x 8Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 V
Data ConvertersA/D 12x10b; D/A 2x8bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case128-QFP
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantEeprom Size-
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3.5
Bus-Released State
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, the CPU halts except for internal operations.
Bus masters other than the CPU may include the direct memory access controller (DMAC) and
data transfer controller (DTC).
For further details, refer to the relevant microcontroller hardware manual.
3.6
Power-Down State
The power-down state includes both modes in which the CPU stops operating and modes in which
the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode,
software standby mode, and hardware standby mode. There are also two other power-down
modes: medium-speed mode and module stop mode. In medium-speed mode the CPU and other
bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation
of individual modules, other than the CPU. For details, refer to the relevant microcontroller
hardware manual.
3.6.1
Sleep Mode
A transition to sleep mode is made if the SLEEP instruction is executed while the software
standby bit (SSBY) in the system control register (SYSCR) is cleared to 0. In sleep mode, CPU
operations stop immediately after execution of the SLEEP instruction. The contents of CPU
registers are retained.
3.6.2
Software Standby Mode
A transition to software standby mode is made if the SLEEP instruction is executed while the
SSBY bit in SYSCR is set to 1. In software standby mode, the CPU and clock halt and all on-chip
operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is
supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain
in their existing states.
Section 3 Processing States
Rev. 4.00 Feb 24, 2006 page 315 of 322
REJ09B0139-0400