HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 226

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Section 2 Instruction Descriptions
2.2.59 (1)
SHLL (B)
SHLL (SHift Logical Left)
Operation
Rd (left logical shift)
Rd
Assembly-Language Format
SHLL.B Rd
Operand Size
Byte
Description
This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the left. The
most significant bit (bit 7) shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.
C
Available Registers
Rd: R0L to R7L, R0H to R7H
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode
Register direct
SHLL.B
Notes
The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag.
Rev. 4.00 Feb 24, 2006 page 210 of 322
REJ09B0139-0400
Condition Code
I
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
cleared to 0.
Z: Set to 1 if the result is zero; otherwise
cleared to 0.
V: Always cleared to 0.
C: Receives the previous value in bit 7.
MSB
. . . . . .
b7
Instruction Format
Operands
1st byte
2nd byte
Rd
1
0
0
Shift Logical
UI H
U
N
Z
V
0
LSB
0
b0
3rd byte
4th byte
rd
C
No. of
States
1

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